From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36421) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VK4WJ-0001yW-BR for qemu-devel@nongnu.org; Thu, 12 Sep 2013 06:53:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VK4WC-0006xc-AT for qemu-devel@nongnu.org; Thu, 12 Sep 2013 06:53:07 -0400 Message-ID: <52319CB4.3010701@cn.fujitsu.com> Date: Thu, 12 Sep 2013 18:51:32 +0800 From: Xie Xianshan MIME-Version: 1.0 References: <522EC970.2000804@cn.fujitsu.com> <523025EF.6010406@cn.fujitsu.com> <52317227.4080706@cn.fujitsu.com> In-Reply-To: Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=UTF-8; format=flowed Subject: Re: [Qemu-devel] Disabling IRQ error List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Max Filippov Cc: qemu-ppc , qemu-devel Dear Max, > Does it mean an IRQ to be edge-triggered? No, it is a level-sensitive and active-high interrupt. This is why i tried to use qemu_irq_raise() to trigger IRQ. Thanks, Simen >> Hi Max, >> Thanks for your patience and help. >> I`ve tried to do what you said, but the problem doesn`t go away. >> And actually i cannot add a new register to the fpga device, because the >> fpga device i`m emulating already exists in the real world. >> So i cannot change anything about hardware properties and linux driver for >> this device. > > Then I don't get its IRQ logic. Does it mean an IRQ to be edge-triggered? > Its model should use qemu_irq_pulse then instead of qemu_irq_raise and > its IRQ line should be connected to edge-sensing input of interrupt controller. > Input that you have used is also used to sense PCI IRQ and is level-sensing. > >> By the way, how did you finally fix your problem? > > I didn't have any. (: >