From: Stephen Warren <swarren@wwwdotorg.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 1/2] Tegra114: Fix PLLX M, N, P init settings
Date: Mon, 23 Sep 2013 15:45:01 -0600 [thread overview]
Message-ID: <5240B65D.2020703@wwwdotorg.org> (raw)
In-Reply-To: <1379966870-4087-1-git-send-email-treding@nvidia.com>
On 09/23/2013 02:07 PM, Thierry Reding wrote:
> From: Jimmy Zhang <jimmzhang@nvidia.com>
>
> The M, N and P width have been changed from Tegra30. The maximum value
> for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
> be set accordingly.
The series,
Acked-by: Stephen Warren <swarren@nvidia.com>
prev parent reply other threads:[~2013-09-23 21:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-23 20:07 [U-Boot] [PATCH v2 1/2] Tegra114: Fix PLLX M, N, P init settings Thierry Reding
2013-09-23 20:07 ` [U-Boot] [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX Thierry Reding
2013-09-30 21:25 ` Tom Warren
2013-10-01 15:06 ` Thierry Reding
2013-10-01 18:02 ` Tom Warren
2013-09-23 21:45 ` Stephen Warren [this message]
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