From: David Daney <ddaney.cavm@gmail.com>
To: Huacai Chen <chenhc@lemote.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
John Crispin <john@phrozen.org>,
linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>,
Hongliang Tao <taohl@lemote.com>, Hua Yan <yanh@lemote.com>
Subject: Re: [PATCH V12 01/12] MIPS: Loongson: Add basic Loongson-3 definition
Date: Wed, 25 Sep 2013 14:17:06 -0700 [thread overview]
Message-ID: <524352D2.10600@gmail.com> (raw)
In-Reply-To: <1380100546-8302-2-git-send-email-chenhc@lemote.com>
On 09/25/2013 02:15 AM, Huacai Chen wrote:
> Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully.
> Loongson-3 has the same IMP field (0x6300) as Loongson-2.
>
> Loongson-3 has a hardware-maintained cache, system software doesn't
> need to maintain coherency.
>
> Loongson-3A is the first revision of Loongson-3, and it is the quad-
> core version of Loongson-2G. Loongson-3A has a simplified version named
> Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
> HyperTransport controller but 2Gq has only one. HT0 is used for cross-
> chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
> cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
> identified as Loongson-3A.
>
> Exsisting Loongson family CPUs:
> Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
> Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
> single-core MIPS CPUs.
> Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
> 64-bit multi-core MIPS CPUs.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: Hongliang Tao <taohl@lemote.com>
> Signed-off-by: Hua Yan <yanh@lemote.com>
> ---
> arch/mips/include/asm/addrspace.h | 6 ++++++
> arch/mips/include/asm/cpu.h | 5 +++--
> arch/mips/include/asm/mach-loongson/spaces.h | 15 +++++++++++++++
> arch/mips/include/asm/module.h | 2 ++
> arch/mips/include/asm/pgtable-bits.h | 7 +++++++
> arch/mips/loongson/Platform | 1 +
> 6 files changed, 34 insertions(+), 2 deletions(-)
> create mode 100644 arch/mips/include/asm/mach-loongson/spaces.h
>
> diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
> index 13d61c0..fdbadf3 100644
> --- a/arch/mips/include/asm/addrspace.h
> +++ b/arch/mips/include/asm/addrspace.h
> @@ -116,7 +116,13 @@
> #define K_CALG_UNCACHED 2
> #define K_CALG_NONCOHERENT 3
> #define K_CALG_COH_EXCL 4
> +
> +#ifdef CONFIG_CPU_LOONGSON3
> +#define K_CALG_COH_SHAREABLE 3
> +#else
> #define K_CALG_COH_SHAREABLE 5
> +#endif
Change this to:
#ifndef K_CALG_COH_SHAREABLE
#define K_CALG_COH_SHAREABLE 5
#endif
This would then be a separate patch from the LOONGSON3 sopecific things.
Then move your LOONGSON3 specific version to spaces.h
> +
> #define K_CALG_NOTUSED 6
> #define K_CALG_UNCACHED_ACCEL 7
>
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index d2035e1..7fffaf1 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -224,6 +224,7 @@
> #define PRID_REV_LOONGSON1B 0x0020
> #define PRID_REV_LOONGSON2E 0x0002
> #define PRID_REV_LOONGSON2F 0x0003
> +#define PRID_REV_LOONGSON3A 0x0005
>
> /*
> * Older processors used to encode processor version and revision in two
> @@ -295,8 +296,8 @@ enum cpu_type_enum {
> * MIPS64 class processors
> */
> CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
> - CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
> - CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
> + CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
> + CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
>
> CPU_LAST
> };
These cpu.h things should probably go into a separate patch.
> diff --git a/arch/mips/include/asm/mach-loongson/spaces.h b/arch/mips/include/asm/mach-loongson/spaces.h
> new file mode 100644
> index 0000000..1e82804
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-loongson/spaces.h
> @@ -0,0 +1,15 @@
> +#ifndef __ASM_MACH_LOONGSON_SPACES_H_
> +#define __ASM_MACH_LOONGSON_SPACES_H_
> +
> +#ifndef CAC_BASE
> +#if defined(CONFIG_64BIT)
> +#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_CPU_LOONGSON3)
> +#define CAC_BASE _AC(0x9800000000000000, UL)
> +#else
> +#define CAC_BASE _AC(0xa800000000000000, UL)
> +#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_CPU_LOONGSON3 */
> +#endif /* CONFIG_64BIT */
> +#endif /* CONFIG_CAC_BASE */
> +
> +#include <asm/mach-generic/spaces.h>
> +#endif
> diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
> index 44b705d..c2edae3 100644
> --- a/arch/mips/include/asm/module.h
> +++ b/arch/mips/include/asm/module.h
> @@ -126,6 +126,8 @@ search_module_dbetables(unsigned long addr)
> #define MODULE_PROC_FAMILY "LOONGSON1 "
> #elif defined CONFIG_CPU_LOONGSON2
> #define MODULE_PROC_FAMILY "LOONGSON2 "
> +#elif defined CONFIG_CPU_LOONGSON3
> +#define MODULE_PROC_FAMILY "LOONGSON3 "
> #elif defined CONFIG_CPU_CAVIUM_OCTEON
> #define MODULE_PROC_FAMILY "OCTEON "
> #elif defined CONFIG_CPU_XLR
> diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
> index 32aea48..6c1e99e 100644
> --- a/arch/mips/include/asm/pgtable-bits.h
> +++ b/arch/mips/include/asm/pgtable-bits.h
> @@ -235,6 +235,13 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
> #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
> #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
>
> +#elif defined(CONFIG_CPU_LOONGSON3)
> +
> +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* LOONGSON */
> +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
> +#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
> +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* LOONGSON */
> +
> #else
>
> #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
> diff --git a/arch/mips/loongson/Platform b/arch/mips/loongson/Platform
> index 29692e5..6205372 100644
> --- a/arch/mips/loongson/Platform
> +++ b/arch/mips/loongson/Platform
> @@ -30,3 +30,4 @@ platform-$(CONFIG_MACH_LOONGSON) += loongson/
> cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely
> load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
> load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
> +load-$(CONFIG_CPU_LOONGSON3) += 0xffffffff80200000
>
next prev parent reply other threads:[~2013-09-25 21:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-25 9:15 [PATCH V12 00/13] MIPS: Add Loongson-3 based machines support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 01/12] MIPS: Loongson: Add basic Loongson-3 definition Huacai Chen
2013-09-25 21:17 ` David Daney [this message]
2013-09-25 9:15 ` [PATCH V12 02/12] MIPS: Loongson: Add basic Loongson-3 CPU support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 03/12] MIPS: Loongson 3: Add Lemote-3A machtypes definition Huacai Chen
2013-09-25 9:15 ` [PATCH V12 04/12] MIPS: Loongson: Add UEFI-like firmware interface support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 05/12] MIPS: Loongson 3: Add HT-linked PCI support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 06/12] MIPS: Loongson 3: Add IRQ init and dispatch support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 07/12] MIPS: Loongson 3: Add serial port support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 08/12] MIPS: Loongson: Add swiotlb to support big memory (>4GB) Huacai Chen
2013-09-25 9:15 ` [PATCH V12 09/12] MIPS: Loongson: Add Loongson-3 Kconfig options Huacai Chen
2013-09-25 21:20 ` David Daney
2013-09-25 9:15 ` [PATCH V12 10/12] MIPS: Loongson 3: Add Loongson-3 SMP support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 11/12] MIPS: Loongson 3: Add CPU hotplug support Huacai Chen
2013-09-25 9:15 ` [PATCH V12 12/12] MIPS: Loongson: Add a Loongson-3 default config file Huacai Chen
2013-09-26 12:45 ` [PATCH V12 00/13] MIPS: Add Loongson-3 based machines support Ralf Baechle
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