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diff for duplicates of <5244C171.2040705@wwwdotorg.org>

diff --git a/a/1.txt b/N1/1.txt
index ce76c53..77ffc34 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,5 +1,5 @@
-On 09/24/2013 03:11 PM, dinguyen at altera.com wrote:
-> From: Dinh Nguyen <dinguyen@altera.com>
+On 09/24/2013 03:11 PM, dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org wrote:
+> From: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
 > 
 > The STMMAC Ethernet controller in SOCFPGA requires setting a register for
 > the phy-mode that is outside of the ethernet IP. This register resides in
@@ -20,3 +20,7 @@ be located, and a register number within its register block too? Or,
 does sysmgr know which register to poke? If so, couldn't the API take
 just a device index rather than a bitmask instead, and calculate the
 mask itself?
+--
+To unsubscribe from this list: send the line "unsubscribe devicetree" in
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diff --git a/a/content_digest b/N1/content_digest
index 34527aa..8b2d7d1 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,12 +1,22 @@
  "ref\01380057120-27108-1-git-send-email-dinguyen@altera.com\0"
- "From\0swarren@wwwdotorg.org (Stephen Warren)\0"
- "Subject\0[PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform\0"
+ "ref\01380057120-27108-1-git-send-email-dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org\0"
+ "From\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>\0"
+ "Subject\0Re: [PATCH 1/2] dts: socfpga: Add ethernet support on Altera's SOCFPGA platform\0"
  "Date\0Thu, 26 Sep 2013 17:21:21 -0600\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org\0"
+ "Cc\0dinh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
+  Pavel Machek <pavel-ynQEQJNshbs@public.gmane.org>
+  Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
+  Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
+  Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
+  Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
+  Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
+  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+ " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0"
  "\00:1\0"
  "b\0"
- "On 09/24/2013 03:11 PM, dinguyen at altera.com wrote:\n"
- "> From: Dinh Nguyen <dinguyen@altera.com>\n"
+ "On 09/24/2013 03:11 PM, dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org wrote:\n"
+ "> From: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>\n"
  "> \n"
  "> The STMMAC Ethernet controller in SOCFPGA requires setting a register for\n"
  "> the phy-mode that is outside of the ethernet IP. This register resides in\n"
@@ -26,6 +36,10 @@
  "be located, and a register number within its register block too? Or,\n"
  "does sysmgr know which register to poke? If so, couldn't the API take\n"
  "just a device index rather than a bitmask instead, and calculate the\n"
- mask itself?
+ "mask itself?\n"
+ "--\n"
+ "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n"
+ "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n"
+ More majordomo info at  http://vger.kernel.org/majordomo-info.html
 
-a8b148fc02483065b01fcc7deebfa9f006c163da55fe6f1a44e1d2a48a2d5454
+20d48b545ddd72bb9bbaae044a3892c63ea8059ac0acdcecb9e7e94094b87a68

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