All of lore.kernel.org
 help / color / mirror / Atom feed
From: Tom Musta <tommusta@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 13/13] Add xxsldwi
Date: Fri, 04 Oct 2013 08:27:05 -0500	[thread overview]
Message-ID: <524EC229.6020507@gmail.com> (raw)
In-Reply-To: <524EBE04.8050207@gmail.com>

This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.

Signed-off-by: Tom Musta <tommusta@gmail.com>
---
  target-ppc/translate.c |   62 
++++++++++++++++++++++++++++++++++++++++++++++++
  1 files changed, 62 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5bab048..2b337ee 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -504,6 +504,7 @@ EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
  EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
  EXTRACT_HELPER(DM, 8, 2);
  EXTRACT_HELPER(UIM, 16, 2);
+EXTRACT_HELPER(SHW, 8, 2);
  /*****************************************************************************/
  /* PowerPC instructions 
table                                                */

@@ -7413,6 +7414,66 @@ static void gen_xxspltw(DisasContext *ctx)
      tcg_temp_free(b2);
  }

+static void gen_xxsldwi(DisasContext *ctx)
+{
+    TCGv_i64 xth, xtl;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    xth = tcg_temp_new();
+    xtl = tcg_temp_new();
+
+    switch (SHW(ctx->opcode)) {
+        case 0: {
+            tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+            tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+            break;
+        }
+        case 1: {
+            TCGv_i64 t0 = tcg_temp_new();
+            tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+            tcg_gen_shli_i64(xth, xth, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xth, xth, t0);
+            tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_shli_i64(xtl, xtl, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xtl, xtl, t0);
+            tcg_temp_free(t0);
+            break;
+        }
+        case 2: {
+            tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+            break;
+        }
+        case 3: {
+            TCGv_i64 t0 = tcg_temp_new();
+            tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+            tcg_gen_shli_i64(xth, xth, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xth, xth, t0);
+            tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+            tcg_gen_shli_i64(xtl, xtl, 32);
+            tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
+            tcg_gen_shri_i64(t0, t0, 32);
+            tcg_gen_or_i64(xtl, xtl, t0);
+            tcg_temp_free(t0);
+            break;
+        }
+    }
+
+    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
+    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
+
+    tcg_temp_free(xth);
+    tcg_temp_free(xtl);
+}
+

  /***                           SPE 
extension                               ***/
  /* Register moves */
@@ -9929,6 +9990,7 @@ VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
  GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
  GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
  GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
+GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),

  #define GEN_XXSEL_ROW(opc3) \
  GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
-- 
1.7.1

      parent reply	other threads:[~2013-10-04 13:27 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-10-04 13:09 [Qemu-devel] [PATCH 00/13] Stage 2 VSX Support Tom Musta
2013-10-04 13:11 ` [Qemu-devel] [PATCH 01/13] Abandon GEN_VSX_* macros Tom Musta
2013-10-04 13:13 ` [Qemu-devel] [PATCH 02/13] Add lxsdx Tom Musta
2013-10-04 13:15 ` [Qemu-devel] [PATCH 03/13] Add lxvdsx Tom Musta
2013-10-04 13:16 ` [Qemu-devel] [PATCH 04/13] Add lxvw4x Tom Musta
2013-10-09 19:54   ` Richard Henderson
2013-10-04 13:17 ` [Qemu-devel] [PATCH 05/13] Add stxsdx Tom Musta
2013-10-04 13:18 ` [Qemu-devel] [PATCH 06/13] Add stxvw4x Tom Musta
2013-10-04 13:20 ` [Qemu-devel] [PATCH 07/13] Add VSX Scalar Move Instructions Tom Musta
2013-10-04 13:21 ` [Qemu-devel] [PATCH 08/13] Add VSX Vector " Tom Musta
2013-10-04 13:22 ` [Qemu-devel] [PATCH 09/13] Add Power7 VSX Logical Instructions Tom Musta
2013-10-04 13:23 ` [Qemu-devel] [PATCH 10/13] Add xxmrgh/xxmrgl Tom Musta
2013-10-09 20:09   ` Richard Henderson
2013-10-10 12:16     ` Tom Musta
2013-10-04 13:24 ` [Qemu-devel] [PATCH 11/13] Add xxsel Tom Musta
2013-10-09 20:13   ` Richard Henderson
2013-10-10 12:27     ` Tom Musta
2013-10-10 13:45       ` Richard Henderson
2013-10-04 13:26 ` [Qemu-devel] [PATCH 12/13] Add xxspltw Tom Musta
2013-10-09 20:19   ` Richard Henderson
2013-10-04 13:27 ` Tom Musta [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=524EC229.6020507@gmail.com \
    --to=tommusta@gmail.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.