From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VUcP7-0000S8-Oj for qemu-devel@nongnu.org; Fri, 11 Oct 2013 09:05:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VUcOz-0000Rk-C7 for qemu-devel@nongnu.org; Fri, 11 Oct 2013 09:05:17 -0400 Message-ID: <5257F76C.7080603@gmail.com> Date: Fri, 11 Oct 2013 08:04:44 -0500 From: Tom Musta MIME-Version: 1.0 References: <5257F4DD.7000204@gmail.com> In-Reply-To: <5257F4DD.7000204@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [v2 09/13] Add Power7 VSX Logical Instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: Tom Musta , qemu-devel@nongnu.org This patch adds the VSX logical instructions that are defined by the Version 2.06 Power ISA (aka Power7): - xxland - xxlandc - xxlor - xxlxor - xxlnor Signed-off-by: Tom Musta --- target-ppc/translate.c | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 03a352d..5056ec9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7276,6 +7276,24 @@ VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) +#define VSX_LOGICAL(name, tcg_op) \ +static void glue(gen_, name)(DisasContext * ctx) \ + { \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ + cpu_vsrh(xB(ctx->opcode))); \ + tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ + cpu_vsrl(xB(ctx->opcode))); \ + } + +VSX_LOGICAL(xxland, tcg_gen_and_tl) +VSX_LOGICAL(xxlandc, tcg_gen_andc_tl) +VSX_LOGICAL(xxlor, tcg_gen_or_tl) +VSX_LOGICAL(xxlxor, tcg_gen_xor_tl) +VSX_LOGICAL(xxlnor, tcg_gen_nor_tl) /*** SPE extension ***/ /* Register moves */ @@ -9779,6 +9797,17 @@ GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), + +#undef VSX_LOGICAL +#define VSX_LOGICAL(name, opc2, opc3, fl2) \ +GEN_XX3FORM(name, opc2, opc3, fl2) + +VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), +VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), +VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), +VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), +VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), + GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), #undef GEN_SPE -- 1.7.1