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diff for duplicates of <525D9532.6080503@gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index 25ede94..2aefcbb 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -5,7 +5,7 @@ On 10/15/13 2:01 PM, Arnd Bergmann wrote:
 >> Hi Arnd,
 >>
 >> On 10/15/13 7:50 AM, Arnd Bergmann wrote:
->>> On Monday 14 October 2013, dinguyen@altera.com wrote:
+>>> On Monday 14 October 2013, dinguyen at altera.com wrote:
 >>>> +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel)
 >>>> +{
 >>>> +       u32 hs_timing;
diff --git a/a/content_digest b/N1/content_digest
index 4574541..94b08b7 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,24 +2,10 @@
  "ref\0201310151450.48650.arnd@arndb.de\0"
  "ref\0525D41AA.7060503@gmail.com\0"
  "ref\0201310152101.44669.arnd@arndb.de\0"
- "From\0Dinh Nguyen <dinh.linux@gmail.com>\0"
- "Subject\0Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager\0"
+ "From\0dinh.linux@gmail.com (Dinh Nguyen)\0"
+ "Subject\0[RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager\0"
  "Date\0Tue, 15 Oct 2013 14:19:14 -0500\0"
- "To\0Arnd Bergmann <arnd@arndb.de>\0"
- "Cc\0dinguyen@altera.com"
-  Pavel Machek <pavel@denx.de>
-  Olof Johansson <olof@lixom.net>
-  Rob Herring <rob.herring@calxeda.com>
-  Pawel Moll <pawel.moll@arm.com>
-  Mark Rutland <mark.rutland@arm.com>
-  Stephen Warren <swarren@wwwdotorg.org>
-  Ian Campbell <ian.campbell@citrix.com>
-  Chris Ball <cjb@laptop.org>
-  Jaehoon Chung <jh80.chung@samsung.com>
-  Seungwon Jeon <tgih.jun@samsung.com>
-  devicetree@vger.kernel.org
-  linux-mmc@vger.kernel.org
- " linux-arm-kernel@lists.infradead.org\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Hi Arnd,\n"
@@ -29,7 +15,7 @@
  ">> Hi Arnd,\n"
  ">>\n"
  ">> On 10/15/13 7:50 AM, Arnd Bergmann wrote:\n"
- ">>> On Monday 14 October 2013, dinguyen@altera.com wrote:\n"
+ ">>> On Monday 14 October 2013, dinguyen at altera.com wrote:\n"
  ">>>> +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel)\n"
  ">>>> +{\n"
  ">>>> +       u32 hs_timing;\n"
@@ -95,4 +81,4 @@
  ">\n"
  "> \tArnd"
 
-bf1a47fe13756aab9adcf5a521dfedcf32a07fddb7bff363e560460ceadff268
+f162b290c97dce04f678d18e9e124669782b66a3103639e38c465f15faa986cb

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