From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-1?Q?Christian_K=F6nig?= Subject: Re: [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Date: Sat, 19 Oct 2013 10:52:38 +0200 Message-ID: <52624856.9040404@vodafone.de> References: <1382128919-29931-1-git-send-email-alexander.deucher@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Content-Transfer-Encoding: quoted-printable Return-path: Received: from smtp-01.vodafone.de (mxout.vodafone.de [80.84.1.40]) by gabe.freedesktop.org (Postfix) with ESMTP id 1E95FE688C for ; Sat, 19 Oct 2013 01:52:41 -0700 (PDT) In-Reply-To: <1382128919-29931-1-git-send-email-alexander.deucher@amd.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Alex Deucher , dri-devel@lists.freedesktop.org Cc: Alex Deucher List-Id: dri-devel@lists.freedesktop.org Am 18.10.2013 22:41, schrieb Alex Deucher: > Needed by the hda driver to properly set up synchronization > on the audio side. > > Signed-off-by: Alex Deucher For both: Reviewed-by: Christian K=F6nig > --- > drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++= ++++++ > drivers/gpu/drm/radeon/evergreend.h | 38 ++++++++++++++++++++++++++= +++++++ > 2 files changed, 75 insertions(+) > > diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/ra= deon/evergreen_hdmi.c > index 5fbe486..abdc893 100644 > --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c > +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c > @@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encod= er *encoder, uint32_t cloc > WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); > } > = > +static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, > + struct drm_display_mode *mode) > +{ > + struct radeon_device *rdev =3D encoder->dev->dev_private; > + struct drm_connector *connector; > + struct radeon_connector *radeon_connector =3D NULL; > + u32 tmp =3D 0; > + > + list_for_each_entry(connector, &encoder->dev->mode_config.connector_lis= t, head) { > + if (connector->encoder =3D=3D encoder) { > + radeon_connector =3D to_radeon_connector(connector); > + break; > + } > + } > + > + if (!radeon_connector) { > + DRM_ERROR("Couldn't find encoder's connector\n"); > + return; > + } > + > + if (mode->flags & DRM_MODE_FLAG_INTERLACE) { > + if (connector->latency_present[1]) > + tmp =3D VIDEO_LIPSYNC(connector->video_latency[1]) | > + AUDIO_LIPSYNC(connector->audio_latency[1]); > + else > + tmp =3D VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); > + } else { > + if (connector->latency_present[0]) > + tmp =3D VIDEO_LIPSYNC(connector->video_latency[0]) | > + AUDIO_LIPSYNC(connector->audio_latency[0]); > + else > + tmp =3D VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); > + } > + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); > +} > + > static void dce4_afmt_write_speaker_allocation(struct drm_encoder *enco= der) > { > struct radeon_device *rdev =3D encoder->dev->dev_private; > @@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encod= er, struct drm_display_mode > dce6_afmt_write_sad_regs(encoder); > } else { > evergreen_hdmi_write_sad_regs(encoder); > + dce4_afmt_write_latency_fields(encoder, mode); > } > = > err =3D drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); > diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon= /evergreend.h > index fa81893..11e002a 100644 > --- a/drivers/gpu/drm/radeon/evergreend.h > +++ b/drivers/gpu/drm/radeon/evergreend.h > @@ -750,6 +750,44 @@ > * bit6 =3D 192 kHz > */ > = > +#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4 > +# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) <= < 0) > +# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) <= < 4) > +/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT > + * 0 =3D use stream header > + * 1-7 =3D channel count - 1 > + */ > +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8 > +# define VIDEO_LIPSYNC(x) (((x) & 0xff) = << 0) > +# define AUDIO_LIPSYNC(x) (((x) & 0xff) = << 8) > +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC > + * 0 =3D invalid > + * x =3D legal delay value > + * 255 =3D sync not supported > + */ > +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec > +# define HBR_CAPABLE (1 << 0) /* en= abled by default */ > + > +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4 > +# define DISPLAY0_TYPE(x) (((x) & 0x3) <= < 0) > +# define DISPLAY_TYPE_NONE 0 > +# define DISPLAY_TYPE_HDMI 1 > +# define DISPLAY_TYPE_DP 2 > +# define DISPLAY0_ID(x) (((x) & 0x3f) = << 2) > +# define DISPLAY1_TYPE(x) (((x) & 0x3) <= < 8) > +# define DISPLAY1_ID(x) (((x) & 0x3f) = << 10) > +# define DISPLAY2_TYPE(x) (((x) & 0x3) <= < 16) > +# define DISPLAY2_ID(x) (((x) & 0x3f) = << 18) > +# define DISPLAY3_TYPE(x) (((x) & 0x3) <= < 24) > +# define DISPLAY3_ID(x) (((x) & 0x3f) = << 26) > +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8 > +# define DISPLAY4_TYPE(x) (((x) & 0x3) <= < 0) > +# define DISPLAY4_ID(x) (((x) & 0x3f) = << 2) > +# define DISPLAY5_TYPE(x) (((x) & 0x3) <= < 8) > +# define DISPLAY5_ID(x) (((x) & 0x3f) = << 10) > +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc > +# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) <= < 0) > + > #define AZ_HOT_PLUG_CONTROL 0x5e78 > # define AZ_FORCE_CODEC_WAKE (1 << 0) > # define PIN0_JACK_DETECTION_ENABLE (1 << 4)