From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-1?Q?Christian_K=F6nig?= Subject: Re: [PATCH] drm/radeon/audio: use actual pll clock for setting up dto Date: Sat, 19 Oct 2013 10:55:29 +0200 Message-ID: <52624901.6080500@vodafone.de> References: <1382139015-2714-1-git-send-email-alexander.deucher@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Content-Transfer-Encoding: quoted-printable Return-path: Received: from smtp-01.vodafone.de (mxout.vodafone.de [80.84.1.40]) by gabe.freedesktop.org (Postfix) with ESMTP id 0AB06E67A5 for ; Sat, 19 Oct 2013 01:55:32 -0700 (PDT) In-Reply-To: <1382139015-2714-1-git-send-email-alexander.deucher@amd.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Alex Deucher , dri-devel@lists.freedesktop.org Cc: Alex Deucher List-Id: dri-devel@lists.freedesktop.org Am 19.10.2013 01:30, schrieb Alex Deucher: > Use the actual pll clock (rather than the mode clock) to set > up the audio dto. This fixes audio playback speed issues > when the pll clock does not exactly match the mode clock. > > Signed-off-by: Alex Deucher Damn, had the same idea while sleeping over it. Patch is: Reviewed-by: Christian K=F6nig > --- > drivers/gpu/drm/radeon/atombios_crtc.c | 2 ++ > drivers/gpu/drm/radeon/evergreen_hdmi.c | 9 +++++---- > drivers/gpu/drm/radeon/r600_hdmi.c | 16 +++++++++------- > drivers/gpu/drm/radeon/radeon_mode.h | 1 + > 4 files changed, 17 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/rad= eon/atombios_crtc.c > index bf87f6d..3a6059f 100644 > --- a/drivers/gpu/drm/radeon/atombios_crtc.c > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c > @@ -1027,6 +1027,8 @@ static void atombios_crtc_set_pll(struct drm_crtc *= crtc, struct drm_display_mode > radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_cloc= k, > &fb_div, &frac_fb_div, &ref_div, &post_div); > = > + radeon_crtc->pll_clock =3D pll_clock * 10; /* convert to khz units */ > + > atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, > radeon_crtc->crtc_id, &radeon_crtc->ss); > = > diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/ra= deon/evergreen_hdmi.c > index 6787365..0d55870 100644 > --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c > +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c > @@ -225,7 +225,7 @@ static void evergreen_hdmi_update_avi_infoframe(struc= t drm_encoder *encoder, > frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); > } > = > -static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clo= ck) > +static void evergreen_audio_set_dto(struct drm_encoder *encoder) > { > struct drm_device *dev =3D encoder->dev; > struct radeon_device *rdev =3D dev->dev_private; > @@ -233,9 +233,10 @@ static void evergreen_audio_set_dto(struct drm_encod= er *encoder, u32 clock) > struct radeon_encoder_atom_dig *dig =3D radeon_encoder->enc_priv; > struct radeon_crtc *radeon_crtc =3D to_radeon_crtc(encoder->crtc); > u32 base_rate =3D 24000; > - u32 max_ratio =3D clock / base_rate; > + u32 max_ratio =3D radeon_crtc->pll_clock / base_rate; > u32 dto_phase; > - u32 dto_modulo =3D clock; > + /* need to use the exact pll clock here to keep audio rate correct */ > + u32 dto_modulo =3D radeon_crtc->pll_clock; > u32 wallclock_ratio; > u32 dto_cntl; > = > @@ -296,7 +297,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encod= er, struct drm_display_mode > return; > offset =3D dig->afmt->offset; > = > - evergreen_audio_set_dto(encoder, mode->clock); > + evergreen_audio_set_dto(encoder); > = > WREG32(HDMI_VBI_PACKET_CONTROL + offset, > HDMI_NULL_SEND); /* send null packets when required */ > diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/= r600_hdmi.c > index 21f2b74..b8c444e 100644 > --- a/drivers/gpu/drm/radeon/r600_hdmi.c > +++ b/drivers/gpu/drm/radeon/r600_hdmi.c > @@ -219,16 +219,18 @@ static void r600_hdmi_audio_workaround(struct drm_e= ncoder *encoder) > value, ~HDMI0_AUDIO_TEST_EN); > } > = > -void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) > +static void r600_audio_set_dto(struct drm_encoder *encoder) > { > struct drm_device *dev =3D encoder->dev; > struct radeon_device *rdev =3D dev->dev_private; > struct radeon_encoder *radeon_encoder =3D to_radeon_encoder(encoder); > struct radeon_encoder_atom_dig *dig =3D radeon_encoder->enc_priv; > + struct radeon_crtc *radeon_crtc =3D to_radeon_crtc(encoder->crtc); > u32 base_rate =3D 24000; > - u32 max_ratio =3D clock / base_rate; > + u32 max_ratio =3D radeon_crtc->pll_clock / base_rate; > u32 dto_phase; > - u32 dto_modulo =3D clock; > + /* need to use the exact pll clock here to keep audio rate correct */ > + u32 dto_modulo =3D radeon_crtc->pll_clock; > u32 wallclock_ratio; > u32 dto_cntl; > = > @@ -279,17 +281,17 @@ void r600_audio_set_dto(struct drm_encoder *encoder= , u32 clock) > */ > if (dig->dig_encoder =3D=3D 0) { > WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); > - WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); > + WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo * 100); > WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ > } else { > WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100); > - WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); > + WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo * 100); > WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ > } > } else { > /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */ > WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | > - AUDIO_DTO_MODULE(clock / 10)); > + AUDIO_DTO_MODULE(dto_modulo / 10)); > } > } > = > @@ -420,7 +422,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, s= truct drm_display_mode *mod > return; > offset =3D dig->afmt->offset; > = > - r600_audio_set_dto(encoder, mode->clock); > + r600_audio_set_dto(encoder); > = > WREG32(HDMI0_VBI_PACKET_CONTROL + offset, > HDMI0_NULL_SEND); /* send null packets when required */ > diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeo= n/radeon_mode.h > index 8b4e712..5b5339b 100644 > --- a/drivers/gpu/drm/radeon/radeon_mode.h > +++ b/drivers/gpu/drm/radeon/radeon_mode.h > @@ -341,6 +341,7 @@ struct radeon_crtc { > u32 wm_low; > u32 wm_high; > struct drm_display_mode hw_mode; > + u32 pll_clock; /* actual clock generated by the pll */ > }; > = > struct radeon_encoder_primary_dac {