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Date: Mon, 21 Oct 2013 18:58:17 +0530
From: Kishon Vijay Abraham I <kishon@ti.com>
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To: Jingoo Han <jg1.han@samsung.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: [QUERY] Number of address translation regions in designware
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Hi,

Currently I see in pcie-designware.c we use only 2 ATU regions. We re-use
INDEX0 for mem outbound and cfg0, and INDEX1 for cfg1 and io. So I'd like to
know if in your platform, do you have only 2 address translation regions? In
DRA7xx we have 16 outbound regions and 4 inbound regions.

Also the same designware IP can be used as a EP also no? Shouldn't we move it
out of drivers/pci/host and allow it to be configured as EP also?

Thanks
Kishon