From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52514) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbaHW-0000oS-KJ for qemu-devel@nongnu.org; Wed, 30 Oct 2013 14:14:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VbaHN-0008N6-SY for qemu-devel@nongnu.org; Wed, 30 Oct 2013 14:14:14 -0400 Received: from mail-qc0-x231.google.com ([2607:f8b0:400d:c01::231]:45931) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbaHN-0008Mz-Ng for qemu-devel@nongnu.org; Wed, 30 Oct 2013 14:14:05 -0400 Received: by mail-qc0-f177.google.com with SMTP id u18so1011027qcx.36 for ; Wed, 30 Oct 2013 11:14:05 -0700 (PDT) Sender: Richard Henderson Message-ID: <52714C69.5030806@twiddle.net> Date: Wed, 30 Oct 2013 11:14:01 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1383073495-5332-1-git-send-email-sebastian@macke.de> <1383073495-5332-10-git-send-email-sebastian@macke.de> In-Reply-To: <1383073495-5332-10-git-send-email-sebastian@macke.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 09/13] target-openrisc: Add CPU which neglects Carry and Overflow Flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sebastian Macke Cc: qemu-devel@nongnu.org, proljc@gmail.com On 10/29/2013 12:04 PM, Sebastian Macke wrote: > The carry and overflag and the instructions l.addc and l.addic > are never used in the toolchain. Linux and gcc compiled software > don't need them. Really? That's quite surprising. > To speed up the emulation a cpu was added which > neglects the flags for l.addi, l.add, l.sub and > generates an illegal instruction error for l.addic and l.addc I'm somewhat shocked that l.addc is never used. To me that points to a missed opportunity in the compiler. It would be much better to simply improve handling of these bits. In a previous patch set you broke out SR[F] to its own variable; I suggest that you do the same for SR[CY] and SR[OV]. If you can implement add et al without branches, the TCG optimizer will be able to do a good job eliminating shadowed computation. A good example to follow here is the ARM implementation. Have a look at the gen_add_CC and gen_sub_CC functions especially. Note that the overflow bit is stored in bit 31 of cpu_VF and the other bits of cpu_VF are ignored. r~