From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ve04s-0005bZ-77 for qemu-devel@nongnu.org; Wed, 06 Nov 2013 05:11:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ve04m-0000ha-LS for qemu-devel@nongnu.org; Wed, 06 Nov 2013 05:11:10 -0500 Received: from mail-qa0-x235.google.com ([2607:f8b0:400d:c00::235]:42862) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ve04m-0000hW-H9 for qemu-devel@nongnu.org; Wed, 06 Nov 2013 05:11:04 -0500 Received: by mail-qa0-f53.google.com with SMTP id k4so1894054qaq.5 for ; Wed, 06 Nov 2013 02:11:04 -0800 (PST) Sender: Paolo Bonzini Message-ID: <527A15B4.9070702@redhat.com> Date: Wed, 06 Nov 2013 11:11:00 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <1383603977-7003-1-git-send-email-hpoussin@reactos.org> In-Reply-To: <1383603977-7003-1-git-send-email-hpoussin@reactos.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 1.7] mips jazz: do not raise data bus exception when accessing invalid addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= Cc: qemu-devel@nongnu.org, Aurelien Jarno Il 04/11/2013 23:26, Hervé Poussineau ha scritto: > MIPS Jazz chipset doesn't seem to raise data bus exceptions on invalid accesses. > However, there is no easy way to prevent them. Creating a big memory region > for the whole address space doesn't prevent memory core to directly call > unassigned_mem_read/write which in turn call cpu->do_unassigned_access, > which (for MIPS CPU) raise an data bus exception. Creating a big MMIO region would work, but it wouldn't let you trap execution accesses. > This fixes a MIPS Jazz regression introduced in c658b94f6e8c206c59d02aa6fbac285b86b53d2c. > > Signed-off-by: Hervé Poussineau > --- > This fixes a known regression in QEMU 1.6. Let it be fixed as soon as possible. > > hw/mips/mips_jazz.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c > index 49bdd02..5f6dd9f 100644 > --- a/hw/mips/mips_jazz.c > +++ b/hw/mips/mips_jazz.c > @@ -108,6 +108,18 @@ static void cpu_request_exit(void *opaque, int irq, int level) > } > } > > +static CPUUnassignedAccess real_do_unassigned_access; > +static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, > + bool is_write, bool is_exec, > + int opaque, unsigned size) > +{ > + if (!is_exec) { > + /* ignore invalid access (ie do not raise exception) */ > + return; > + } > + (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); > +} > + > static void mips_jazz_init(MemoryRegion *address_space, > MemoryRegion *address_space_io, > ram_addr_t ram_size, > @@ -117,6 +129,7 @@ static void mips_jazz_init(MemoryRegion *address_space, > char *filename; > int bios_size, n; > MIPSCPU *cpu; > + CPUClass *cc; > CPUMIPSState *env; > qemu_irq *rc4030, *i8259; > rc4030_dma *dmas; > @@ -154,6 +167,17 @@ static void mips_jazz_init(MemoryRegion *address_space, > env = &cpu->env; > qemu_register_reset(main_cpu_reset, cpu); > > + /* Chipset returns 0 in invalid reads and do not raise data exceptions. > + * However, we can't simply add a global memory region to catch > + * everything, as memory core directly call unassigned_mem_read/write > + * on some invalid accesses, which call do_unassigned_access on the > + * CPU, which raise an exception. > + * Handle that case by hijacking the do_unassigned_access method on > + * the CPU, and do not raise exceptions for data access. */ > + cc = CPU_GET_CLASS(cpu); > + real_do_unassigned_access = cc->do_unassigned_access; > + cc->do_unassigned_access = mips_jazz_do_unassigned_access; > + > /* allocate RAM */ > memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size); > vmstate_register_ram_global(ram); > Reviewed-by: Paolo Bonzini Please remember to add 1.7 in the subject at this time. Paolo