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Date: Tue, 12 Nov 2013 05:25:11 +1000
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Subject: Re: [Qemu-devel] [RFC] target-arm: provide skeleton for a64 insn
	decoding
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To: Claudio Fontana <claudio.fontana@linaro.org>, Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, Michael Matz <matz@suse.de>, Alex Bennee <alex.bennee@linaro.org>, Alexander Graf <agraf@suse.de>, patches@linaro.org

On 11/12/2013 01:13 AM, Claudio Fontana wrote:
> +/* C3.2 Branches, exception generating and system instructions */
> +static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
> +{
> +    switch (extract32(insn, 25, 7)) {
> +    case 0x0a: case 0x4a: /* Unconditional branch (immediate) */
> +        disas_uncond_b_imm(s, insn);
> +        break;

Bit 25 is "-" for unconditional branch, so this entry should be

 0x0a, 0x0b, 0x4a, 0x4b

All of the other decodings look good.


r~