From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Richter <thor@math.tu-berlin.de>
Subject: Watermark computation on i830 - potential bug?
Date: Sat, 16 Nov 2013 21:57:43 +0100
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References: <10422_1384614100_528788D4_10422_10146_1_1384614124-3929-1-git-send-email-daniel.vetter@ffwll.ch>
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To: intel-gfx@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>
List-Id: intel-gfx@lists.freedesktop.org

Hi Daniel, dear intel experts,

as reported yesterday, the watermark levels - the values of the FW_BLC 
register are completely off on my R31. This renders the display unusable 
after Daniel's patch from Friday, both the internal and the external. 
The fwater_lo values for planes A and B need to be *at least* 6, while 
the current algorithm sets them to one. Thus, the display flickers (now 
constantly) because the watermark values are wrong.

I now checked the code in intel_pm.c and I wonder how that actually 
works. The display becomes in my experiments *more stable* if I increase 
the watermark register value (i.e. FW_BLC), thus higher values refer to 
a higher watermark, i.e. the chipset starts fetching data earlier. So 
far my observation.

However, the way how intel_calculate_wm is written, it subtracts the 
number of necessary entries from the fifo size, and thus is written 
under the assumption that the FIFO drains in the direction of increasing 
entries. Thus, for the model used in intel_calculate_wm, *higher values* 
indicate a *lower watermark*, i.e. would instruct the
DMA engine to fetch data later.

This is in contradiction to my observation where higher values indicate
an *earlier* (and not a later) fetch.

Thus, is the definition of the FW_BLC register possibly simply wrong? Or 
is the subtraction in intel_calculate_wm possibly wrong?

Thanks,
	Thomas