From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViQg4-00058S-Ex for qemu-devel@nongnu.org; Mon, 18 Nov 2013 10:23:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ViQfy-0007wr-81 for qemu-devel@nongnu.org; Mon, 18 Nov 2013 10:23:52 -0500 Received: from ssl.dlhnet.de ([91.198.192.8]:35731 helo=ssl.dlh.net) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViQfx-0007wh-VV for qemu-devel@nongnu.org; Mon, 18 Nov 2013 10:23:46 -0500 Message-ID: <528A310A.60607@dlhnet.de> Date: Mon, 18 Nov 2013 16:23:54 +0100 From: Peter Lieven MIME-Version: 1.0 References: <1379694292-1601-1-git-send-email-pbonzini@redhat.com> <1379694292-1601-12-git-send-email-pbonzini@redhat.com> In-Reply-To: <1379694292-1601-12-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL 11/13] target-i386: forward CPUID cache leaves when -cpu host is used List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: =?UTF-8?B?QmVub8OudCBDYW5ldA==?= I do not know, but this patch might introduce a regression. If I specify: -smp 2,sockets=3D1,cores=3D2,threads=3D1 to a Windows 2012 = R2 Server it crashes at boot time. -smp 2 works. git bisect start # good: [62ecc3a0e3c77a4944c92a02dd7fae2ab1f2290d] Update VERSION for 1.6= .1 release git bisect good 62ecc3a0e3c77a4944c92a02dd7fae2ab1f2290d # bad: [964668b03d26f0b5baa5e5aff0c966f4fcb76e9e] Update version for 1.7.= 0-rc0 release git bisect bad 964668b03d26f0b5baa5e5aff0c966f4fcb76e9e # good: [1ee2daeb6448312d6d0e22175f5c1b9b01f8974c] Update version for 1.6= .0 git bisect good 1ee2daeb6448312d6d0e22175f5c1b9b01f8974c # bad: [03cfd8faa7ffb7201e2949b99c2f35b1fef7078b] linux-user: add support= of binfmt_misc 'O' flag git bisect bad 03cfd8faa7ffb7201e2949b99c2f35b1fef7078b # good: [5a93d5c2abc719bd44f6c9fbeed88d3cae712606] Merge remote-tracking = branch 'mjt/trivial-patches' into staging git bisect good 5a93d5c2abc719bd44f6c9fbeed88d3cae712606 # good: [a27292b5d7545509bfa171922516d2033c570205] virtio-scsi: Make type= virtio-scsi-common abstract git bisect good a27292b5d7545509bfa171922516d2033c570205 # good: [469936ae0a9891b2de7e46743f683535b0819bee] target-i386: Fix segme= nt cache dump git bisect good 469936ae0a9891b2de7e46743f683535b0819bee # bad: [3e4be9c29784df09c364b52a55e826a0b05b950e] Merge remote-tracking b= ranch 'qemu-kvm/uq/master' into staging git bisect bad 3e4be9c29784df09c364b52a55e826a0b05b950e # good: [2571f8f5fbaea5dc3bdcd84737f109b459576e90] Merge remote-tracking = branch 'spice/spice.v74' into staging git bisect good 2571f8f5fbaea5dc3bdcd84737f109b459576e90 # good: [c5daeae1b4ddff97d605bd954a7c2a2b2cf6040f] linux-headers: update = to 3.11 git bisect good c5daeae1b4ddff97d605bd954a7c2a2b2cf6040f # good: [ceae18bd74e8940ff79935a257c72e665b084bcc] lsi: add 53C810 varian= t git bisect good ceae18bd74e8940ff79935a257c72e665b084bcc # bad: [f010bc643a2759e87e989c3e4e85f15ec71ae98f] target-i386: add featur= e kvm_pv_unhalt git bisect bad f010bc643a2759e87e989c3e4e85f15ec71ae98f # bad: [4f2656079f903efcd0d8224cbc79170ad3ee5b70] linux-headers: update t= o 3.12-rc1 git bisect bad 4f2656079f903efcd0d8224cbc79170ad3ee5b70 # bad: [787aaf5703a702094f395db6795e74230282cd62] target-i386: forward CP= UID cache leaves when -cpu host is used git bisect bad 787aaf5703a702094f395db6795e74230282cd62 Peter On 20.09.2013 18:24, Paolo Bonzini wrote: > From: Beno=C3=AEt Canet > > Some users running cpu intensive tasks checking the cache CPUID leaves = at > startup and making decisions based on the result reported that the gues= t was > not reflecting the host CPUID leaves when -cpu host is used. > > This patch fix this. > > Signed-off-by: Beno=C3=AEt Canet > [Rename new field to cache_info_passthrough - Paolo] > Signed-off-by: Paolo Bonzini > --- > target-i386/cpu-qom.h | 3 +++ > target-i386/cpu.c | 19 +++++++++++++++++++ > 2 files changed, 22 insertions(+) > > diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h > index c4447c2..f4fab15 100644 > --- a/target-i386/cpu-qom.h > +++ b/target-i386/cpu-qom.h > @@ -70,6 +70,9 @@ typedef struct X86CPU { > bool hyperv_relaxed_timing; > int hyperv_spinlock_attempts; > =20 > + /* if true the CPUID code directly forward host cache leaves to th= e guest */ > + bool cache_info_passthrough; > + > /* Features that were filtered out because of missing host capabi= lities */ > uint32_t filtered_features[FEATURE_WORDS]; > =20 > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index c36345e..46edd75 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -486,6 +486,7 @@ typedef struct x86_def_t { > int stepping; > FeatureWordArray features; > char model_id[48]; > + bool cache_info_passthrough; > } x86_def_t; > =20 > #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) > @@ -1139,6 +1140,7 @@ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_= def) > assert(kvm_enabled()); > =20 > x86_cpu_def->name =3D "host"; > + x86_cpu_def->cache_info_passthrough =3D true; > host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); > x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx); > =20 > @@ -1888,6 +1890,7 @@ static void cpu_x86_register(X86CPU *cpu, const c= har *name, Error **errp) > env->features[FEAT_C000_0001_EDX] =3D def->features[FEAT_C000_000= 1_EDX]; > env->features[FEAT_7_0_EBX] =3D def->features[FEAT_7_0_EBX]; > env->cpuid_xlevel2 =3D def->xlevel2; > + cpu->cache_info_passthrough =3D def->cache_info_passthrough; > =20 > object_property_set_str(OBJECT(cpu), def->model_id, "model-id", e= rrp); > } > @@ -2062,6 +2065,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t in= dex, uint32_t count, > break; > case 2: > /* cache info: needed for Pentium Pro compatibility */ > + if (cpu->cache_info_passthrough) { > + host_cpuid(index, 0, eax, ebx, ecx, edx); > + break; > + } > *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ > *ebx =3D 0; > *ecx =3D 0; > @@ -2071,6 +2078,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t in= dex, uint32_t count, > break; > case 4: > /* cache info: needed for Core compatibility */ > + if (cpu->cache_info_passthrough) { > + host_cpuid(index, count, eax, ebx, ecx, edx); > + break; > + } > if (cs->nr_cores > 1) { > *eax =3D (cs->nr_cores - 1) << 26; > } else { > @@ -2228,6 +2239,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t in= dex, uint32_t count, > break; > case 0x80000005: > /* cache info (L1 cache) */ > + if (cpu->cache_info_passthrough) { > + host_cpuid(index, 0, eax, ebx, ecx, edx); > + break; > + } > *eax =3D (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16= ) | \ > (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); > *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16= ) | \ > @@ -2239,6 +2254,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t in= dex, uint32_t count, > break; > case 0x80000006: > /* cache info (L2 cache) */ > + if (cpu->cache_info_passthrough) { > + host_cpuid(index, 0, eax, ebx, ecx, edx); > + break; > + } > *eax =3D (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \ > (L2_DTLB_2M_ENTRIES << 16) | \ > (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \