From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= Subject: Re: [PATCH 1/2] pvh: clearly specify used parameters in vcpu_guest_context Date: Wed, 20 Nov 2013 11:29:05 +0100 Message-ID: <528C8EF1.5090201@citrix.com> References: <1384864488-5194-1-git-send-email-roger.pau@citrix.com> <1384864488-5194-2-git-send-email-roger.pau@citrix.com> <528B768C0200007800104810@nat28.tlf.novell.com> <528B7DF5.1000603@citrix.com> <528B93260200007800104972@nat28.tlf.novell.com> <528B94F6.3090804@citrix.com> <528BA59D0200007800104ABD@nat28.tlf.novell.com> <528C7E54.7030106@citrix.com> <528C8ECA0200007800104EA4@nat28.tlf.novell.com> <528C82C8.3080103@citrix.com> <528C94D50200007800104EFD@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------020801030003080800040506" Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Vj520-0003oL-E9 for xen-devel@lists.xenproject.org; Wed, 20 Nov 2013 10:29:12 +0000 In-Reply-To: <528C94D50200007800104EFD@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: George Dunlap , xen-devel@lists.xenproject.org, Keir Fraser , Tim Deegan List-Id: xen-devel@lists.xenproject.org --------------020801030003080800040506 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit On 20/11/13 10:54, Jan Beulich wrote: >>>> On 20.11.13 at 10:37, Roger Pau Monné wrote: >> On 20/11/13 10:28, Jan Beulich wrote: >>>>>> On 20.11.13 at 10:18, Roger Pau Monné wrote: >>>> On 19/11/13 17:53, Jan Beulich wrote: >>>>>>>> On 19.11.13 at 17:42, Roger Pau Monné wrote: >>>>>> Trying to make all those fields functional on PVH (or HVM) is quite >>>>>> useless IMHO, it's going to add more code that I doubt anyone is going >>>>>> to use when you can instead use the bare metal functions to set all >>>>>> those things (and from an OS point of view it's also more comfortable >>>>>> because you need less Xen specific stuff). >>>>> >>>>> That last part I certainly agree to, but that would apply to CR0 >>>>> and CR4 just as much. >>>> >>>> I've removed the usage of anything that's not strictly necessary in >>>> order to do AP bringup, so I've removed the setting of debugregs: >>> >>> You can't - this code is also used for HVM guests. >> >> Yes, my fault, I erroneously thought this was introduced by 35b1e076, >> but it has been there longer than that. Would you agree to a patch >> similar to the one posted, but without touching the setting of debugregs? > > Yes, if Mukesh and George confirm that this is not going to break > things. Here it is: --- >>From dc19632f361b2737791821232ce9b38508f1cd7f Mon Sep 17 00:00:00 2001 From: Roger Pau Monne Date: Thu, 14 Nov 2013 18:07:51 +0100 Subject: [PATCH v3] pvh: clearly specify used parameters in vcpu_guest_context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The aim of this patch is to define a stable way in which PVH is going to do AP bringup. Since we are running inside of a HVM container, PVH should only need to set flags, cr3 and user_regs in order to bring up a vCPU, the rest can be set once the vCPU is started using the bare metal methods. Signed-off-by: Roger Pau Monné Cc: George Dunlap Cc: Mukesh Rathor Cc: Jan Beulich Cc: Tim Deegan Cc: Keir Fraser --- xen/arch/x86/domain.c | 13 +++++-------- xen/arch/x86/hvm/vmx/vmx.c | 6 +----- xen/include/asm-x86/hvm/hvm.h | 6 +++--- xen/include/public/arch-x86/xen.h | 6 ++---- 4 files changed, 11 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index a3868f9..c0ac5d6 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -704,9 +704,12 @@ int arch_set_info_guest( /* PVH 32bitfixme */ ASSERT(!compat); - if ( c(ctrlreg[1]) || c(ldt_base) || c(ldt_ents) || + if ( c(ctrlreg[0]) || c(ctrlreg[1]) || c(ctrlreg[2]) || + c(ctrlreg[4]) || c(ctrlreg[5]) || c(ctrlreg[6]) || + c(ctrlreg[7]) || c(ldt_base) || c(ldt_ents) || c(user_regs.cs) || c(user_regs.ss) || c(user_regs.es) || c(user_regs.ds) || c(user_regs.fs) || c(user_regs.gs) || + c(kernel_ss) || c(kernel_sp) || c.nat->gs_base_kernel || c.nat->gdt_ents || c.nat->fs_base || c.nat->gs_base_user ) return -EINVAL; } @@ -745,13 +748,7 @@ int arch_set_info_guest( if ( has_hvm_container_vcpu(v) ) { - /* - * NB: TF_kernel_mode is set unconditionally for HVM guests, - * so we always use the gs_base_kernel here. If we change this - * function to imitate the PV functionality, we'll need to - * make it pay attention to the kernel bit. - */ - hvm_set_info_guest(v, compat ? 0 : c.nat->gs_base_kernel); + hvm_set_info_guest(v); if ( is_hvm_vcpu(v) || v->is_initialised ) goto out; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index f0132a4..8d923e7 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1467,7 +1467,7 @@ static int vmx_event_pending(struct vcpu *v) return intr_info & INTR_INFO_VALID_MASK; } -static void vmx_set_info_guest(struct vcpu *v, uint64_t gs_base_kernel) +static void vmx_set_info_guest(struct vcpu *v) { unsigned long intr_shadow; @@ -1492,10 +1492,6 @@ static void vmx_set_info_guest(struct vcpu *v, uint64_t gs_base_kernel) __vmwrite(GUEST_INTERRUPTIBILITY_INFO, intr_shadow); } - /* PVH 32bitfixme */ - if ( is_pvh_vcpu(v) ) - __vmwrite(GUEST_GS_BASE, gs_base_kernel); - vmx_vmcs_exit(v); } diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h index a8ba06d..ccca5df 100644 --- a/xen/include/asm-x86/hvm/hvm.h +++ b/xen/include/asm-x86/hvm/hvm.h @@ -160,7 +160,7 @@ struct hvm_function_table { int (*msr_write_intercept)(unsigned int msr, uint64_t msr_content); void (*invlpg_intercept)(unsigned long vaddr); void (*handle_cd)(struct vcpu *v, unsigned long value); - void (*set_info_guest)(struct vcpu *v, uint64_t gs_base_kernel); + void (*set_info_guest)(struct vcpu *v); void (*set_rdtsc_exiting)(struct vcpu *v, bool_t); /* Nested HVM */ @@ -434,10 +434,10 @@ void *hvm_map_guest_frame_rw(unsigned long gfn, bool_t permanent); void *hvm_map_guest_frame_ro(unsigned long gfn, bool_t permanent); void hvm_unmap_guest_frame(void *p, bool_t permanent); -static inline void hvm_set_info_guest(struct vcpu *v, uint64_t gs_base_kernel) +static inline void hvm_set_info_guest(struct vcpu *v) { if ( hvm_funcs.set_info_guest ) - return hvm_funcs.set_info_guest(v, gs_base_kernel); + return hvm_funcs.set_info_guest(v); } int hvm_debug_op(struct vcpu *v, int32_t op); diff --git a/xen/include/public/arch-x86/xen.h b/xen/include/public/arch-x86/xen.h index 5d220ce..f35804b 100644 --- a/xen/include/public/arch-x86/xen.h +++ b/xen/include/public/arch-x86/xen.h @@ -161,10 +161,8 @@ typedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */ * - For HVM guests, the structures read include: fpu_ctxt (if * VGCT_I387_VALID is set), flags, user_regs, debugreg[*] * - * - PVH guests are the same as HVM guests, but additionally set cr3, - * and for 64-bit guests, gs_base_kernel. Additionally, the following - * entries must be 0: ctrlreg[1], ldt_base, ldt_ents, user_regs.{cs, - * ss, es, ds, fs, gs), gdt_ents, fs_base, and gs_base_user. + * - PVH guests are the same as HVM guests, but additionally use ctrlreg[3] to + * set cr3. All other fields not used should be set to 0. */ struct vcpu_guest_context { /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */ -- 1.7.7.5 (Apple Git-26) --------------020801030003080800040506 Content-Type: text/plain; charset="UTF-8"; x-mac-type=0; x-mac-creator=0; name="0001-pvh-clearly-specify-used-parameters-in-vcpu_guest_co.patch" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename*0="0001-pvh-clearly-specify-used-parameters-in-vcpu_guest_co.pa"; filename*1="tch" RnJvbSBkYzE5NjMyZjM2MWIyNzM3NzkxODIxMjMyY2U5YjM4NTA4ZjFjZDdmIE1vbiBTZXAg MTcgMDA6MDA6MDAgMjAwMQpGcm9tOiBSb2dlciBQYXUgTW9ubmUgPHJvZ2VyLnBhdUBjaXRy aXguY29tPgpEYXRlOiBUaHUsIDE0IE5vdiAyMDEzIDE4OjA3OjUxICswMTAwClN1YmplY3Q6 IFtQQVRDSCB2M10gcHZoOiBjbGVhcmx5IHNwZWNpZnkgdXNlZCBwYXJhbWV0ZXJzIGluCiB2 Y3B1X2d1ZXN0X2NvbnRleHQKTUlNRS1WZXJzaW9uOiAxLjAKQ29udGVudC1UeXBlOiB0ZXh0 L3BsYWluOyBjaGFyc2V0PVVURi04CkNvbnRlbnQtVHJhbnNmZXItRW5jb2Rpbmc6IDhiaXQK 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