From mboxrd@z Thu Jan 1 00:00:00 1970 Message-ID: <52956FA6.8020705@ti.com> Date: Wed, 27 Nov 2013 09:35:58 +0530 From: Sekhar Nori MIME-Version: 1.0 To: "ivan.khoronzhuk" , "Shilimkar, Santosh" , Rob Landley , Russell King Subject: Re: [PATCH 07/12] memory: davinci-aemif: introduce AEMIF driver References: <1384187188-5776-1-git-send-email-ivan.khoronzhuk@ti.com>, <1384187188-5776-8-git-send-email-ivan.khoronzhuk@ti.com> <4F5844B3A985794BA902E12C070812375F8D2E@DNCE04.ent.ti.com> <52944BD3.90105@ti.com> <5294DE17.9080900@ti.com> In-Reply-To: <5294DE17.9080900@ti.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Cc: Mark Rutland , "devicetree@vger.kernel.org" , "Strashko, Grygorii" , Pawel Moll , Ian Campbell , Stephen Warren , Kumar Gala , Rob Herring , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tuesday 26 November 2013 11:14 PM, ivan.khoronzhuk wrote: >>> +static int davinci_aemif_probe(struct platform_device *pdev) >>> +{ >>> + int ret = -ENODEV, i; >>> + struct resource *res; >>> + struct device *dev = &pdev->dev; >>> + struct device_node *np = dev->of_node; >>> + >>> + if (np == NULL) >>> + return 0; >>> + >>> + if (aemif) { >>> + dev_err(dev, "davinci_aemif driver is in use currently\n"); >>> + return -EBUSY; >>> + } >> >> Why expressly prevent multiple AEMIF devices? Its entirely conceivable >> to have two memories like NAND and NOR flash connect to two different >> AEMIF interfaces. >> > > It can be, but I'm not sure if it is needed. Currently I've not seen case where > more than 2 cses were used, I mean we have 2 cs free, why do we need the second AEMIF > controller? One usual reason is pinmux constraints. Its probably not a concern on the device you are working with right now but as devices get smaller, functionality on pins is multiplexed to handle multiple different use cases. Thanks, Sekhar From mboxrd@z Thu Jan 1 00:00:00 1970 From: nsekhar@ti.com (Sekhar Nori) Date: Wed, 27 Nov 2013 09:35:58 +0530 Subject: [PATCH 07/12] memory: davinci-aemif: introduce AEMIF driver In-Reply-To: <5294DE17.9080900@ti.com> References: <1384187188-5776-1-git-send-email-ivan.khoronzhuk@ti.com>, <1384187188-5776-8-git-send-email-ivan.khoronzhuk@ti.com> <4F5844B3A985794BA902E12C070812375F8D2E@DNCE04.ent.ti.com> <52944BD3.90105@ti.com> <5294DE17.9080900@ti.com> Message-ID: <52956FA6.8020705@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tuesday 26 November 2013 11:14 PM, ivan.khoronzhuk wrote: >>> +static int davinci_aemif_probe(struct platform_device *pdev) >>> +{ >>> + int ret = -ENODEV, i; >>> + struct resource *res; >>> + struct device *dev = &pdev->dev; >>> + struct device_node *np = dev->of_node; >>> + >>> + if (np == NULL) >>> + return 0; >>> + >>> + if (aemif) { >>> + dev_err(dev, "davinci_aemif driver is in use currently\n"); >>> + return -EBUSY; >>> + } >> >> Why expressly prevent multiple AEMIF devices? Its entirely conceivable >> to have two memories like NAND and NOR flash connect to two different >> AEMIF interfaces. >> > > It can be, but I'm not sure if it is needed. Currently I've not seen case where > more than 2 cses were used, I mean we have 2 cs free, why do we need the second AEMIF > controller? One usual reason is pinmux constraints. Its probably not a concern on the device you are working with right now but as devices get smaller, functionality on pins is multiplexed to handle multiple different use cases. Thanks, Sekhar From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sekhar Nori Subject: Re: [PATCH 07/12] memory: davinci-aemif: introduce AEMIF driver Date: Wed, 27 Nov 2013 09:35:58 +0530 Message-ID: <52956FA6.8020705@ti.com> References: <1384187188-5776-1-git-send-email-ivan.khoronzhuk@ti.com>, <1384187188-5776-8-git-send-email-ivan.khoronzhuk@ti.com> <4F5844B3A985794BA902E12C070812375F8D2E@DNCE04.ent.ti.com> <52944BD3.90105@ti.com> <5294DE17.9080900@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <5294DE17.9080900@ti.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+gldm-linux-mtd-36=gmane.org@lists.infradead.org To: "ivan.khoronzhuk" , "Shilimkar, Santosh" , Rob Landley , Russell King Cc: Mark Rutland , "devicetree@vger.kernel.org" , "Strashko, Grygorii" , Pawel Moll , Ian Campbell , Stephen Warren , Kumar Gala , Rob Herring , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org On Tuesday 26 November 2013 11:14 PM, ivan.khoronzhuk wrote: >>> +static int davinci_aemif_probe(struct platform_device *pdev) >>> +{ >>> + int ret = -ENODEV, i; >>> + struct resource *res; >>> + struct device *dev = &pdev->dev; >>> + struct device_node *np = dev->of_node; >>> + >>> + if (np == NULL) >>> + return 0; >>> + >>> + if (aemif) { >>> + dev_err(dev, "davinci_aemif driver is in use currently\n"); >>> + return -EBUSY; >>> + } >> >> Why expressly prevent multiple AEMIF devices? Its entirely conceivable >> to have two memories like NAND and NOR flash connect to two different >> AEMIF interfaces. >> > > It can be, but I'm not sure if it is needed. Currently I've not seen case where > more than 2 cses were used, I mean we have 2 cs free, why do we need the second AEMIF > controller? One usual reason is pinmux constraints. Its probably not a concern on the device you are working with right now but as devices get smaller, functionality on pins is multiplexed to handle multiple different use cases. Thanks, Sekhar ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754307Ab3K0EHg (ORCPT ); Tue, 26 Nov 2013 23:07:36 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:44807 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753464Ab3K0EH2 (ORCPT ); Tue, 26 Nov 2013 23:07:28 -0500 Message-ID: <52956FA6.8020705@ti.com> Date: Wed, 27 Nov 2013 09:35:58 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.1 MIME-Version: 1.0 To: "ivan.khoronzhuk" , "Shilimkar, Santosh" , Rob Landley , Russell King CC: Mark Rutland , "devicetree@vger.kernel.org" , "Strashko, Grygorii" , Pawel Moll , Stephen Warren , Ian Campbell , Kumar Gala , Rob Herring , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH 07/12] memory: davinci-aemif: introduce AEMIF driver References: <1384187188-5776-1-git-send-email-ivan.khoronzhuk@ti.com>, <1384187188-5776-8-git-send-email-ivan.khoronzhuk@ti.com> <4F5844B3A985794BA902E12C070812375F8D2E@DNCE04.ent.ti.com> <52944BD3.90105@ti.com> <5294DE17.9080900@ti.com> In-Reply-To: <5294DE17.9080900@ti.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 26 November 2013 11:14 PM, ivan.khoronzhuk wrote: >>> +static int davinci_aemif_probe(struct platform_device *pdev) >>> +{ >>> + int ret = -ENODEV, i; >>> + struct resource *res; >>> + struct device *dev = &pdev->dev; >>> + struct device_node *np = dev->of_node; >>> + >>> + if (np == NULL) >>> + return 0; >>> + >>> + if (aemif) { >>> + dev_err(dev, "davinci_aemif driver is in use currently\n"); >>> + return -EBUSY; >>> + } >> >> Why expressly prevent multiple AEMIF devices? Its entirely conceivable >> to have two memories like NAND and NOR flash connect to two different >> AEMIF interfaces. >> > > It can be, but I'm not sure if it is needed. Currently I've not seen case where > more than 2 cses were used, I mean we have 2 cs free, why do we need the second AEMIF > controller? One usual reason is pinmux constraints. Its probably not a concern on the device you are working with right now but as devices get smaller, functionality on pins is multiplexed to handle multiple different use cases. Thanks, Sekhar