From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlZxN-0000Uu-RF for qemu-devel@nongnu.org; Wed, 27 Nov 2013 02:54:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VlZxJ-0007Q6-7E for qemu-devel@nongnu.org; Wed, 27 Nov 2013 02:54:45 -0500 Received: from [222.73.24.84] (port=4231 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlZxI-0007Pg-IV for qemu-devel@nongnu.org; Wed, 27 Nov 2013 02:54:41 -0500 Message-ID: <5295A4D4.4080401@cn.fujitsu.com> Date: Wed, 27 Nov 2013 15:52:52 +0800 From: Li Guang MIME-Version: 1.0 References: <1385530609-22741-1-git-send-email-lig.fnst@cn.fujitsu.com> <1385530609-22741-3-git-send-email-lig.fnst@cn.fujitsu.com> In-Reply-To: Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=ISO-8859-1; format=flowed Subject: Re: [Qemu-devel] [PATCH v5 2/5] hw/timer: add sunxi timer device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: Peter Maydell , "qemu-devel@nongnu.org Developers" Peter Crosthwaite wrote: > On Wed, Nov 27, 2013 at 3:36 PM, liguang wrote: > >> Signed-off-by: liguang >> --- >> default-configs/arm-softmmu.mak | 2 + >> hw/timer/Makefile.objs | 1 + >> hw/timer/sunxi-pit.c | 276 +++++++++++++++++++++++++++++++++++++++ >> include/hw/timer/sunxi-pit.h | 37 +++++ >> 4 files changed, 316 insertions(+), 0 deletions(-) >> create mode 100644 hw/timer/sunxi-pit.c >> create mode 100644 include/hw/timer/sunxi-pit.h >> >> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak >> index a555eef..7bf5ad0 100644 >> --- a/default-configs/arm-softmmu.mak >> +++ b/default-configs/arm-softmmu.mak >> @@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y >> >> CONFIG_SDHCI=y >> CONFIG_INTEGRATOR_DEBUG=y >> + >> +CONFIG_SUNXI_PIT=y >> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs >> index eca5905..f7888e9 100644 >> --- a/hw/timer/Makefile.objs >> +++ b/hw/timer/Makefile.objs >> @@ -27,3 +27,4 @@ obj-$(CONFIG_SH4) += sh_timer.o >> obj-$(CONFIG_TUSB6010) += tusb6010.o >> >> obj-$(CONFIG_MC146818RTC) += mc146818rtc.o >> +obj-$(CONFIG_SUNXI_PIT) += sunxi-pit.o >> diff --git a/hw/timer/sunxi-pit.c b/hw/timer/sunxi-pit.c >> new file mode 100644 >> index 0000000..36eb13c >> --- /dev/null >> +++ b/hw/timer/sunxi-pit.c >> @@ -0,0 +1,276 @@ >> +/* >> + * Allwinner sunxi timer device emulation >> + * >> + * Copyright (C) 2013 Li Guang >> + * Written by Li Guang >> + * >> + * This program is free software; you can redistribute it and/or modify it >> + * under the terms of the GNU General Public License as published by the >> + * Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + * >> + * This program is distributed in the hope that it will be useful, but WITHOUT >> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or >> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License >> + * for more details. >> + */ >> + >> +#include "hw/sysbus.h" >> +#include "hw/ptimer.h" >> +#include "sysemu/sysemu.h" >> +#include "hw/timer/sunxi-pit.h" >> + >> + >> +typedef struct SunxiPITState { >> + /*< private>*/ >> + SysBusDevice parent_obj; >> + /*< public>*/ >> + qemu_irq irq[SUNXI_TIMER_NR]; >> + ptimer_state *timer[SUNXI_TIMER_NR]; >> + MemoryRegion iomem; >> + >> + uint32_t irq_enable; >> + uint32_t irq_status; >> + uint32_t control[SUNXI_TIMER_NR]; >> + uint32_t interval[SUNXI_TIMER_NR]; >> + uint32_t count[SUNXI_TIMER_NR]; >> + uint32_t watch_dog_mode; >> + uint32_t watch_dog_control; >> + uint32_t count_lo; >> + uint32_t count_hi; >> + uint32_t count_ctl; >> +} SunxiPITState; >> > So i've done some more list reasearch. If you want this to work with > the latest SoC style device model layout, you need to move this struct > definition to the device header file, so container object can embed it > with their container state structs. Check the arm mpcore and its > subcomponents (e.g. mptimer) for a very modern example. > > >> + >> +static uint64_t sunxi_pit_read(void *opaque, hwaddr offset, unsigned size) >> +{ >> + SunxiPITState *s = SUNXI_PIT(opaque); >> + uint8_t index; >> + >> + switch (offset) { >> + case SUNXI_TIMER_IRQ_EN: >> + return s->irq_enable; >> + break; >> > break after return not needed. Does this throw a werror? Fix globally. > > >> + case SUNXI_TIMER_IRQ_ST: >> + return s->irq_status; >> + break; >> + case SUNXI_TIMER_BASE ... SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT: >> + index = offset& 0xf0; >> + index>>= 4; >> + index -= 1; >> + switch (offset& 0x0f) { >> + case SUNXI_TIMER_CONTROL: >> + return s->control[index]; >> + break; >> + case SUNXI_TIMER_INTERVAL: >> + return s->interval[index]; >> + break; >> + case SUNXI_TIMER_COUNT: >> + s->count[index] = ptimer_get_count(s->timer[index]); >> + return s->count[index]; >> + default: >> + break; >> > This is also a guest error condition. Same in write(). > > > will fix all. Thanks! Li Guang