[U-Boot] [PATCH] powerpc/mpc85xx: Add support for single source clocking

[York Sun <yorksun@freescale.com>]

On 11/27/2013 09:34 PM, Priyanka Jain wrote:
> Single-source clocking is new feature introduced in T1040.
> In this mode, a differential clock is supplied to the
> DIFF_SYSCLK_P/N inputs to the processor, which in turn is
> used to supply clocks to the sysclock, ddrclock and usbclock.
> 
> So, both ddrclock and syclock are driven by same differential
> sysclock in single-sourec clocking whereas in normal clocking
> mode, generally separate DDRCLK and SYSCLK pins provides
> reference clock for sysclock and ddrclock
> 
> DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
> -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
>  normal clocking mode by DDR_Reference clock
> 
> -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
>  single source clocking mode by DIFF_SYSCLK
> 
> Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
> 
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> ---
>  arch/powerpc/cpu/mpc85xx/speed.c          |   20 ++++++++++++++++++++
>  arch/powerpc/include/asm/config_mpc85xx.h |    1 +
>  arch/powerpc/include/asm/immap_85xx.h     |    3 +++
>  3 files changed, 24 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
> index 1a58a19..cd49695 100644
> --- a/arch/powerpc/cpu/mpc85xx/speed.c
> +++ b/arch/powerpc/cpu/mpc85xx/speed.c
> @@ -77,7 +77,27 @@ void get_sys_info(sys_info_t *sys_info)
>  
>  	sys_info->freq_systembus = sysclk;
>  #ifdef CONFIG_DDR_CLK_FREQ

Do you think it is right to put the single clock detection here? This
macro CONFIG_DDR_CLK_FREQ is used when a dedicated DDR reference clock
is used. In case the DIFF_SYSCLK is used, you don't have to have a DDR
reference clock, do you?

> +#ifdef CONFIG_SINGLE_SOURCE_CLK
> +	/*
> +	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
> +	 * are driven by separate DDR Refclock or single source
> +	 * differential clock.
> +	 */
> +	uint single_src;
> +	single_src = (in_be32(&gur->rcwsr[5]) >>
> +		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
> +		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
> +	/*
> +	 * For single source clocking, both ddrclock and syclock
> +	 * are driven by differential sysclock.
> +	 */
> +	if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
> +		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
> +	else
> +		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
> +#else
>  	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
> +#endif
>  #else
>  	sys_info->freq_ddrbus = sysclk;
>  #endif

My point is you probably don't have to define CONFIG_DDR_CLK_FREQ to use
single source clock.

York