* [PATCH] clk: tegra: Correct clock number for UARTE @ 2013-12-02 11:30 ` Thierry Reding 0 siblings, 0 replies; 10+ messages in thread From: Thierry Reding @ 2013-12-02 11:30 UTC (permalink / raw) To: Peter De Schrijver Cc: Mike Turquette, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-tegra-u79uwXL29TY76Z2rM5mHXA UARTE has clock number 66. Number 65 is the right one for UARTD. Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 5c35885f4a7c..3744a6fe589e 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), -- 1.8.4.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH] clk: tegra: Correct clock number for UARTE @ 2013-12-02 11:30 ` Thierry Reding 0 siblings, 0 replies; 10+ messages in thread From: Thierry Reding @ 2013-12-02 11:30 UTC (permalink / raw) To: linux-arm-kernel UARTE has clock number 66. Number 65 is the right one for UARTD. Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 5c35885f4a7c..3744a6fe589e 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), -- 1.8.4.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
[parent not found: <1385983825-20317-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH] clk: tegra: Correct clock number for UARTE 2013-12-02 11:30 ` Thierry Reding @ 2013-12-02 11:47 ` Lucas Stach -1 siblings, 0 replies; 10+ messages in thread From: Lucas Stach @ 2013-12-02 11:47 UTC (permalink / raw) To: Thierry Reding Cc: Peter De Schrijver, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Mike Turquette, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Am Montag, den 02.12.2013, 12:30 +0100 schrieb Thierry Reding: > UARTE has clock number 66. Number 65 is the right one for UARTD. > > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > index 5c35885f4a7c..3744a6fe589e 100644 > --- a/drivers/clk/tegra/clk-tegra-periph.c > +++ b/drivers/clk/tegra/clk-tegra-periph.c > @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { > UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), > UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), > UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), > - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), > + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), > XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), > XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), > XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), Is this a stable patch or why are those magic numbers even necessary? I have to admit I didn't follow the Tegra clk stuff closely, but with all the churn going on there I would have suspected that those numbers would have been replaced by the DT include defines by now. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] clk: tegra: Correct clock number for UARTE @ 2013-12-02 11:47 ` Lucas Stach 0 siblings, 0 replies; 10+ messages in thread From: Lucas Stach @ 2013-12-02 11:47 UTC (permalink / raw) To: linux-arm-kernel Am Montag, den 02.12.2013, 12:30 +0100 schrieb Thierry Reding: > UARTE has clock number 66. Number 65 is the right one for UARTD. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > index 5c35885f4a7c..3744a6fe589e 100644 > --- a/drivers/clk/tegra/clk-tegra-periph.c > +++ b/drivers/clk/tegra/clk-tegra-periph.c > @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { > UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), > UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), > UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), > - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), > + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), > XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), > XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), > XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), Is this a stable patch or why are those magic numbers even necessary? I have to admit I didn't follow the Tegra clk stuff closely, but with all the churn going on there I would have suspected that those numbers would have been replaced by the DT include defines by now. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 10+ messages in thread
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* Re: [PATCH] clk: tegra: Correct clock number for UARTE 2013-12-02 11:47 ` Lucas Stach @ 2013-12-02 12:14 ` Thierry Reding -1 siblings, 0 replies; 10+ messages in thread From: Thierry Reding @ 2013-12-02 12:14 UTC (permalink / raw) To: Lucas Stach Cc: Peter De Schrijver, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Mike Turquette, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r [-- Attachment #1: Type: text/plain, Size: 2405 bytes --] On Mon, Dec 02, 2013 at 12:47:27PM +0100, Lucas Stach wrote: > Am Montag, den 02.12.2013, 12:30 +0100 schrieb Thierry Reding: > > UARTE has clock number 66. Number 65 is the right one for UARTD. > > > > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > --- > > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > > index 5c35885f4a7c..3744a6fe589e 100644 > > --- a/drivers/clk/tegra/clk-tegra-periph.c > > +++ b/drivers/clk/tegra/clk-tegra-periph.c > > @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { > > UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), > > UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), > > UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), > > - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), > > + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), > > XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), > > XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), > > XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), > > Is this a stable patch or why are those magic numbers even necessary? I > have to admit I didn't follow the Tegra clk stuff closely, but with all > the churn going on there I would have suspected that those numbers would > have been replaced by the DT include defines by now. There is no 1:1 mapping between the DT include defines and the hardware clock numbers. For instance, UARTB has DT define 192, but the enable bit is at offset 7. I think the main reason for doing was because of the Tegra-specific reset API. Now that that's being converted to the generic API, there may be some room to refactor this. Until then I think we're stuck with having these numbers in this table. But perhaps there were other reasons to do this as well. Peter or Stephen may know the details better than I do. Thierry [-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] clk: tegra: Correct clock number for UARTE @ 2013-12-02 12:14 ` Thierry Reding 0 siblings, 0 replies; 10+ messages in thread From: Thierry Reding @ 2013-12-02 12:14 UTC (permalink / raw) To: linux-arm-kernel On Mon, Dec 02, 2013 at 12:47:27PM +0100, Lucas Stach wrote: > Am Montag, den 02.12.2013, 12:30 +0100 schrieb Thierry Reding: > > UARTE has clock number 66. Number 65 is the right one for UARTD. > > > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > --- > > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > > index 5c35885f4a7c..3744a6fe589e 100644 > > --- a/drivers/clk/tegra/clk-tegra-periph.c > > +++ b/drivers/clk/tegra/clk-tegra-periph.c > > @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { > > UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), > > UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), > > UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), > > - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), > > + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), > > XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), > > XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), > > XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), > > Is this a stable patch or why are those magic numbers even necessary? I > have to admit I didn't follow the Tegra clk stuff closely, but with all > the churn going on there I would have suspected that those numbers would > have been replaced by the DT include defines by now. There is no 1:1 mapping between the DT include defines and the hardware clock numbers. For instance, UARTB has DT define 192, but the enable bit is at offset 7. I think the main reason for doing was because of the Tegra-specific reset API. Now that that's being converted to the generic API, there may be some room to refactor this. Until then I think we're stuck with having these numbers in this table. But perhaps there were other reasons to do this as well. Peter or Stephen may know the details better than I do. Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20131202/cfee0d39/attachment-0001.sig> ^ permalink raw reply [flat|nested] 10+ messages in thread
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* Re: [PATCH] clk: tegra: Correct clock number for UARTE 2013-12-02 12:14 ` Thierry Reding @ 2013-12-02 12:34 ` Peter De Schrijver -1 siblings, 0 replies; 10+ messages in thread From: Peter De Schrijver @ 2013-12-02 12:34 UTC (permalink / raw) To: Thierry Reding Cc: Lucas Stach, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Mike Turquette, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On Mon, Dec 02, 2013 at 01:14:48PM +0100, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Mon, Dec 02, 2013 at 12:47:27PM +0100, Lucas Stach wrote: > > Am Montag, den 02.12.2013, 12:30 +0100 schrieb Thierry Reding: > > > UARTE has clock number 66. Number 65 is the right one for UARTD. > > > > > > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > > --- > > > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > > > index 5c35885f4a7c..3744a6fe589e 100644 > > > --- a/drivers/clk/tegra/clk-tegra-periph.c > > > +++ b/drivers/clk/tegra/clk-tegra-periph.c > > > @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { > > > UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), > > > UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), > > > UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), > > > - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), > > > + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), > > > XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), > > > XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), > > > XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), > > > > Is this a stable patch or why are those magic numbers even necessary? I > > have to admit I didn't follow the Tegra clk stuff closely, but with all > > the churn going on there I would have suspected that those numbers would > > have been replaced by the DT include defines by now. > > There is no 1:1 mapping between the DT include defines and the hardware > clock numbers. For instance, UARTB has DT define 192, but the enable bit > is at offset 7. > Indeed. Some clocks share the enable bit (eg UARTB and VFIR) and hence the hardware 'clock number'. The hardware 'clock number' really only tells you the bank number and the bit in the clk_enable/disable/state register. The bank number is just 'clock number' / 32. bit number is 'clock number' % 32. > I think the main reason for doing was because of the Tegra-specific > reset API. Now that that's being converted to the generic API, there may > be some room to refactor this. Until then I think we're stuck with > having these numbers in this table. > It's still a rather convenient way I think. An alternative would be to specify the bit number and the bank ID as 2 separate parameters. Cheers, Peter. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] clk: tegra: Correct clock number for UARTE @ 2013-12-02 12:34 ` Peter De Schrijver 0 siblings, 0 replies; 10+ messages in thread From: Peter De Schrijver @ 2013-12-02 12:34 UTC (permalink / raw) To: linux-arm-kernel On Mon, Dec 02, 2013 at 01:14:48PM +0100, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Mon, Dec 02, 2013 at 12:47:27PM +0100, Lucas Stach wrote: > > Am Montag, den 02.12.2013, 12:30 +0100 schrieb Thierry Reding: > > > UARTE has clock number 66. Number 65 is the right one for UARTD. > > > > > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > > --- > > > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > > > index 5c35885f4a7c..3744a6fe589e 100644 > > > --- a/drivers/clk/tegra/clk-tegra-periph.c > > > +++ b/drivers/clk/tegra/clk-tegra-periph.c > > > @@ -492,7 +492,7 @@ static struct tegra_periph_init_data periph_clks[] = { > > > UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), > > > UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), > > > UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), > > > - UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte), > > > + UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), > > > XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), > > > XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), > > > XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), > > > > Is this a stable patch or why are those magic numbers even necessary? I > > have to admit I didn't follow the Tegra clk stuff closely, but with all > > the churn going on there I would have suspected that those numbers would > > have been replaced by the DT include defines by now. > > There is no 1:1 mapping between the DT include defines and the hardware > clock numbers. For instance, UARTB has DT define 192, but the enable bit > is at offset 7. > Indeed. Some clocks share the enable bit (eg UARTB and VFIR) and hence the hardware 'clock number'. The hardware 'clock number' really only tells you the bank number and the bit in the clk_enable/disable/state register. The bank number is just 'clock number' / 32. bit number is 'clock number' % 32. > I think the main reason for doing was because of the Tegra-specific > reset API. Now that that's being converted to the generic API, there may > be some room to refactor this. Until then I think we're stuck with > having these numbers in this table. > It's still a rather convenient way I think. An alternative would be to specify the bit number and the bank ID as 2 separate parameters. Cheers, Peter. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] clk: tegra: Correct clock number for UARTE 2013-12-02 11:30 ` Thierry Reding @ 2013-12-03 19:57 ` Stephen Warren -1 siblings, 0 replies; 10+ messages in thread From: Stephen Warren @ 2013-12-03 19:57 UTC (permalink / raw) To: Thierry Reding, Peter De Schrijver Cc: Mike Turquette, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-tegra-u79uwXL29TY76Z2rM5mHXA On 12/02/2013 04:30 AM, Thierry Reding wrote: > UARTE has clock number 66. Number 65 is the right one for UARTD. Reviewed-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] clk: tegra: Correct clock number for UARTE @ 2013-12-03 19:57 ` Stephen Warren 0 siblings, 0 replies; 10+ messages in thread From: Stephen Warren @ 2013-12-03 19:57 UTC (permalink / raw) To: linux-arm-kernel On 12/02/2013 04:30 AM, Thierry Reding wrote: > UARTE has clock number 66. Number 65 is the right one for UARTD. Reviewed-by: Stephen Warren <swarren@nvidia.com> ^ permalink raw reply [flat|nested] 10+ messages in thread
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2013-12-02 11:30 [PATCH] clk: tegra: Correct clock number for UARTE Thierry Reding
2013-12-02 11:30 ` Thierry Reding
[not found] ` <1385983825-20317-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-12-02 11:47 ` Lucas Stach
2013-12-02 11:47 ` Lucas Stach
[not found] ` <1385984847.4086.3.camel-WzVe3FnzCwFR6QfukMTsflXZhhPuCNm+@public.gmane.org>
2013-12-02 12:14 ` Thierry Reding
2013-12-02 12:14 ` Thierry Reding
[not found] ` <20131202121447.GB12793-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2013-12-02 12:34 ` Peter De Schrijver
2013-12-02 12:34 ` Peter De Schrijver
2013-12-03 19:57 ` Stephen Warren
2013-12-03 19:57 ` Stephen Warren
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