From mboxrd@z Thu Jan 1 00:00:00 1970 Message-ID: <529ED29C.1030208@st.com> Date: Wed, 4 Dec 2013 06:58:36 +0000 From: Angus Clark MIME-Version: 1.0 To: Huang Shijie Subject: Re: [PATCH 0/4] mtd: spi-nor: add a new framework for SPI NOR References: <1385447575-23773-1-git-send-email-b32955@freescale.com> <20131127043253.GA9468@ld-irv-0074.broadcom.com> <5298AA23.7080404@st.com> <529E976E.4050104@freescale.com> In-Reply-To: <529E976E.4050104@freescale.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Cc: marex@denx.de, broonie@linaro.org, dwmw2@infradead.org, Linus Walleij , linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, pekon@ti.com, sourav.poddar@ti.com, Brian Norris , Lee Jones , linux-arm-kernel@lists.infradead.org List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 12/04/2013 02:46 AM, Huang Shijie wrote: > 于 2013年11月29日 22:52, Angus Clark 写道: >> int (*write_reg)(struct spi_nor_info *info, >> uint8_t cmd, uint8_t *reg, int len, >> int wren, int wtr); > I guess you add the 'wren' for the issuing write-enable before issuing > the 'cmd'. > > but what's 'wtr' for? i do not know what's the meaning of the 'wtr'. > 'wtr' is for "Wait 'til Ready". Some register writes are instant, while others require polling of the "Write In Progress" bit. Cheers, Angus From mboxrd@z Thu Jan 1 00:00:00 1970 From: Angus Clark Subject: Re: [PATCH 0/4] mtd: spi-nor: add a new framework for SPI NOR Date: Wed, 4 Dec 2013 06:58:36 +0000 Message-ID: <529ED29C.1030208@st.com> References: <1385447575-23773-1-git-send-email-b32955@freescale.com> <20131127043253.GA9468@ld-irv-0074.broadcom.com> <5298AA23.7080404@st.com> <529E976E.4050104@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Brian Norris , , , Lee Jones , Linus Walleij , , , , , , To: Huang Shijie Return-path: In-Reply-To: <529E976E.4050104-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Sender: linux-spi-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-ID: On 12/04/2013 02:46 AM, Huang Shijie wrote: > =E4=BA=8E 2013=E5=B9=B411=E6=9C=8829=E6=97=A5 22:52, Angus Clark =E5=86= =99=E9=81=93: >> int (*write_reg)(struct spi_nor_info *info, >> uint8_t cmd, uint8_t *reg, int len, >> int wren, int wtr); > I guess you add the 'wren' for the issuing write-enable before issuin= g > the 'cmd'. >=20 > but what's 'wtr' for? i do not know what's the meaning of the 'wtr'. >=20 'wtr' is for "Wait 'til Ready". Some register writes are instant, whil= e others require polling of the "Write In Progress" bit. Cheers, Angus -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: angus.clark@st.com (Angus Clark) Date: Wed, 4 Dec 2013 06:58:36 +0000 Subject: [PATCH 0/4] mtd: spi-nor: add a new framework for SPI NOR In-Reply-To: <529E976E.4050104@freescale.com> References: <1385447575-23773-1-git-send-email-b32955@freescale.com> <20131127043253.GA9468@ld-irv-0074.broadcom.com> <5298AA23.7080404@st.com> <529E976E.4050104@freescale.com> Message-ID: <529ED29C.1030208@st.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/04/2013 02:46 AM, Huang Shijie wrote: > ? 2013?11?29? 22:52, Angus Clark ??: >> int (*write_reg)(struct spi_nor_info *info, >> uint8_t cmd, uint8_t *reg, int len, >> int wren, int wtr); > I guess you add the 'wren' for the issuing write-enable before issuing > the 'cmd'. > > but what's 'wtr' for? i do not know what's the meaning of the 'wtr'. > 'wtr' is for "Wait 'til Ready". Some register writes are instant, while others require polling of the "Write In Progress" bit. Cheers, Angus