From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46017) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vo9Gz-0004WK-0o for qemu-devel@nongnu.org; Wed, 04 Dec 2013 05:01:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vo9Gs-0000EB-32 for qemu-devel@nongnu.org; Wed, 04 Dec 2013 05:01:36 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:60789) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vo9Gr-0000Di-Tv for qemu-devel@nongnu.org; Wed, 04 Dec 2013 05:01:30 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MXA0049N16E2730@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Wed, 04 Dec 2013 10:01:26 +0000 (GMT) Message-id: <529EFD75.7020208@samsung.com> Date: Wed, 04 Dec 2013 14:01:25 +0400 From: Fedorov Sergey MIME-version: 1.0 References: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com> <1386060535-15908-6-git-send-email-s.fedorov@samsung.com> In-reply-to: Content-type: text/plain; charset=UTF-8; format=flowed Content-transfer-encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Peter Crosthwaite Cc: Johannes Winter , a.basov@samsung.com, "qemu-devel@nongnu.org Developers" , Svetlana Fedoseeva On 12/03/2013 04:51 PM, Peter Maydell wrote: > On 3 December 2013 12:20, Peter Crosthwaite > wrote: >> On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote: >>> From: Svetlana Fedoseeva >>> >>> Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM >>> state info. Provide CPU mode name for monitor mode. >>> >>> Signed-off-by: Svetlana Fedoseeva >>> Signed-off-by: Sergey Fedorov >>> --- >>> target-arm/cpu.h | 7 ++++--- >>> target-arm/helper.c | 3 +++ >>> target-arm/machine.c | 12 ++++++------ >>> target-arm/translate.c | 2 +- >>> 4 files changed, 14 insertions(+), 10 deletions(-) >>> >>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >>> index 0b93e39..94d8bd1 100644 >>> --- a/target-arm/cpu.h >>> +++ b/target-arm/cpu.h >>> @@ -124,9 +124,9 @@ typedef struct CPUARMState { >>> uint32_t spsr; >>> >>> /* Banked registers. */ >>> - uint32_t banked_spsr[6]; >>> - uint32_t banked_r13[6]; >>> - uint32_t banked_r14[6]; >>> + uint32_t banked_spsr[7]; >>> + uint32_t banked_r13[7]; >>> + uint32_t banked_r14[7]; >>> >> Are there any more modes yet to be implemented? It might save on >> future VMSD version bumps if we just pad this out to its ultimate >> value now. > The remaining mode defined for AArch32 which we don't > implement yet is Hyp mode, which has a banked R13 and SPSR, > but not a banked LR. > > -- PMM > > So should a number of banked core registers be increased more? Personally, I'd like to keep this patch only TZ-related. Best regards, Sergey Fedorov