From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48062) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vo9Np-0000tn-5A for qemu-devel@nongnu.org; Wed, 04 Dec 2013 05:08:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vo9Ng-0002zQ-IS for qemu-devel@nongnu.org; Wed, 04 Dec 2013 05:08:41 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:61225) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vo9Ng-0002zK-C5 for qemu-devel@nongnu.org; Wed, 04 Dec 2013 05:08:32 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MXA005BY1I6DT30@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Wed, 04 Dec 2013 10:08:30 +0000 (GMT) Message-id: <529EFF1C.1010701@samsung.com> Date: Wed, 04 Dec 2013 14:08:28 +0400 From: Fedorov Sergey MIME-version: 1.0 References: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com> In-reply-to: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com> Content-type: text/plain; charset=ISO-8859-1; format=flowed Content-transfer-encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 00/21] target-arm: add CPU core TrustZone support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Sergey Fedorov , a.basov@samsung.com, johannes.winter@iaik.tugraz.at On 12/03/2013 12:48 PM, Sergey Fedorov wrote: > This patch set implements a basic support of CPU core TrustZone feature. The > following major functionalities are implemented: > * CPU monitor mode > * Separate code translation for each secure state > * CPACR & NSACR co-processor access control > * Separate TLB for each secure state > * Co-processor register banking > * SMC instruction > * FIQ/IRQ routing to monitor mode > > There is no support for banked co-processor register migration, save/load its > VM state yet. That is an open question how to implement this functionality. Any > suggestions is greatly appreciated. > > This patch set is a request for comments for the proof of concept. > > Sergey Fedorov (18): > target-arm: move SCR & VBAR into TrustZone register list > target-arm: adjust TTBCR for TrustZone feature > target-arm: add arm_is_secure() helper > target-arm: reject switching to monitor mode from non-secure state > target-arm: adjust arm_current_pl() for TrustZone > target-arm: adjust SCR CP15 register access rights > target-arm: add non-secure Translation Block flag > target-arm: implement CPACR register logic > target-arm: add NSACR support > target-arm: add SDER definition > target-arm: split TLB for secure state > target-arm: add banked coprocessor register type > target-arm: convert appropriate coprocessor registers to banked type > target-arm: use c13_context field for CONTEXTIDR > target-arm: switch banked CP registers > target-arm: add MVBAR support > target-arm: implement SMC instruction > target-arm: implement IRQ/FIQ routing to Monitor mode > > Svetlana Fedoseeva (3): > target-arm: add TrustZone CPU feature > target-arm: preserve RAO/WI bits of ARMv7 SCTLR > target-arm: add CPU Monitor mode > > target-arm/cpu.c | 6 +- > target-arm/cpu.h | 126 ++++++++++++---- > target-arm/helper.c | 308 +++++++++++++++++++++++++++++--------- > target-arm/machine.c | 12 +- > target-arm/translate.c | 388 ++++++++++++++++++++++++++++++------------------ > target-arm/translate.h | 2 + > 6 files changed, 585 insertions(+), 257 deletions(-) > We'd like this patch series finally to be merged into mainstream. What should be done to achieve this goal? Best regards, Sergey Fedorov