From: Stephen Warren <swarren@wwwdotorg.org>
To: Ashwini Ghuge <aghuge@nvidia.com>,
rob.herring@calxeda.com, pawel.moll@arm.com,
mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
rob@landley.net, linus.walleij@linaro.org,
grant.likely@linaro.org, linux-tegra@vger.kernel.org,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org
Subject: Re: [PATCH] pinctrl: tegra124: add pinctrl driver for NVIDIA's Tegra124 SoC
Date: Wed, 04 Dec 2013 12:30:48 -0700 [thread overview]
Message-ID: <529F82E8.3000206@wwwdotorg.org> (raw)
In-Reply-To: <1384191718-16817-1-git-send-email-aghuge@nvidia.com>
On 11/11/2013 10:41 AM, Ashwini Ghuge wrote:
> The driver uses the common Tegra pinctrl driver utility functions to
> implement the majority of the driver. It is based on the similar Tegra114
> pinctrl
> +static const struct tegra_function tegra124_functions[] = {
...
> + FUNCTION(i2c1),
> + FUNCTION(i2c2),
> + FUNCTION(i2c3),
> + FUNCTION(i2c4),
> + FUNCTION(i2cpwr),
Is that complete? Tegra124 apparently has 6 I2C controllers. Are the
pins for the new sixth controller (0x7000d100) not affected by the pinmux?
prev parent reply other threads:[~2013-12-04 19:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-11 17:41 [PATCH] pinctrl: tegra124: add pinctrl driver for NVIDIA's Tegra124 SoC Ashwini Ghuge
2013-11-11 18:01 ` Mark Rutland
[not found] ` <20131111180124.GA27735-NuALmloUBlrZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2013-11-11 18:24 ` Stephen Warren
[not found] ` <528120EF.1030000-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-11-12 9:19 ` Mark Rutland
2013-12-04 19:30 ` Stephen Warren [this message]
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