From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kleber Sacilotto de Souza Subject: Re: [PATCH] drm/radeon: Disable writeback by default on ppc Date: Wed, 04 Dec 2013 20:16:05 -0200 Message-ID: <529FA9A5.4060706@linux.vnet.ibm.com> References: <1371477978-25440-1-git-send-email-ajax@redhat.com> <1371485240.13840.78.camel@localhost> <1383863356.4776.202.camel@pasglop> <527CEA7D.4060704@linux.vnet.ibm.com> <1385334947.4882.153.camel@pasglop> <5293E73E.8050704@linux.vnet.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from e24smtp02.br.ibm.com (e24smtp02.br.ibm.com [32.104.18.86]) by gabe.freedesktop.org (Postfix) with ESMTP id EEA9DFBEB1 for ; Wed, 4 Dec 2013 14:16:11 -0800 (PST) Received: from /spool/local by e24smtp02.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 4 Dec 2013 20:16:09 -0200 Received: from d24relay03.br.ibm.com (d24relay03.br.ibm.com [9.13.184.25]) by d24dlp01.br.ibm.com (Postfix) with ESMTP id 3F9B23520064 for ; Wed, 4 Dec 2013 17:16:06 -0500 (EST) Received: from d24av03.br.ibm.com (d24av03.br.ibm.com [9.8.31.95]) by d24relay03.br.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id rB4MFoHV41549912 for ; Wed, 4 Dec 2013 20:15:50 -0200 Received: from d24av03.br.ibm.com (localhost [127.0.0.1]) by d24av03.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id rB4MG5EE018956 for ; Wed, 4 Dec 2013 20:16:06 -0200 In-Reply-To: <5293E73E.8050704@linux.vnet.ibm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org To: Benjamin Herrenschmidt , Jerome Glisse , Alex Deucher Cc: Brian King , Thadeu Lima de Souza Cascardo , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On 11/25/2013 10:11 PM, Kleber Sacilotto de Souza wrote: > On 11/24/2013 09:15 PM, Benjamin Herrenschmidt wrote: >> On Fri, 2013-11-08 at 11:43 -0200, Kleber Sacilotto de Souza wrote: >>> On 11/07/2013 08:29 PM, Benjamin Herrenschmidt wrote: >>>> On Mon, 2013-06-17 at 18:57 -0400, Alex Deucher wrote: >>>> >>>>> Weird. I wonder if there is an issue with cache snoops on PPC. We >>>>> currently use the gart in cached mode (GPU snoops CPU cache) with >>>>> cached pages. I wonder if we need to use uncached pages on PPC. >>>> There is no such issue and no known bugs with DMA writes on those >>>> PCIe host bridges (and they do get hammered pretty bad here). >>>> >>>> This needs further investigation by the lab/hw guys to find out what's >>>> actually happening on the bus and the host bridge. >>>> >>>> Thadeu, Kleber: Jerome suggested writing a test case in userspace that >>>> continuously writes to a spare scratch register (thus triggering the >>>> corresponding writeback DMA) and checks the memory location to compare >>>> the writeback value (using a debugfs file for example, or mmap). I was not able to reproduce the issue with this method, even after a weekend run. However, doing some more investigation it seems the problem is here, where we read the ring rptr: u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, struct radeon_ring *ring) { u32 rptr; if (rdev->wb.enabled) rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); else rptr = RREG32(ring->rptr_reg); return rptr; } I realized that the DMA'ed rptr value has always the opposite byte order from the MMIO value. Since RREG32 already returns the register value on the CPU byte order, it seems we don't need to byte-swap the DMA'ed value. If I remove the le32_to_cpu() call and use the DMA'ed value directly, I don't get the IB scheduling failures and piglit results are the same as with writeback disabled. Is the adapter chipset swapping the bytes before doing the DMA to a big-endian host? -- Kleber Sacilotto de Souza IBM Linux Technology Center