From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, "Michael Matz" <matz@suse.de>,
"C Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu
Subject: Re: [Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for B and BL insns
Date: Fri, 06 Dec 2013 08:34:34 +1300 [thread overview]
Message-ID: <52A0D54A.6050406@twiddle.net> (raw)
In-Reply-To: <1386247180-26994-9-git-send-email-peter.maydell@linaro.org>
On 12/06/2013 01:39 AM, Peter Maydell wrote:
> From: Alexander Graf <agraf@suse.de>
>
> Implement the B and BL instructions (PC relative branches and calls).
>
> For convenience in managing TCG temporaries which might be generated
> if a source register is the zero-register XZR, we provide a simple
> mechanism for creating a new temp which is automatically freed at the
> end of decode of the instruction.
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
> [claudio: renamed functions, adapted to new decoder layout]
> Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/translate-a64.c | 64 ++++++++++++++++++++++++++++++++++++++++++--
> target-arm/translate.h | 3 +++
> 2 files changed, 65 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2013-12-05 19:34 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-05 12:39 [Qemu-devel] [PATCH v3 00/12] target-arm: A64 decoder, foundation plus branches Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 01/12] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 02/12] target-arm: A64: add set_pc cpu method Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 03/12] target-arm: A64: provide functions for accessing FPCR and FPSR Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 04/12] target-arm: Support fp registers in gdb stub Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 05/12] target-arm: A64: add stubs for a64 specific helpers Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 06/12] target-arm: A64: provide skeleton for a64 insn decoding Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 07/12] target-arm: A64: expand decoding skeleton for system instructions Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for B and BL insns Peter Maydell
2013-12-05 19:34 ` Richard Henderson [this message]
2013-12-09 13:49 ` Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 09/12] target-arm: A64: add support for BR, BLR and RET insns Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 10/12] target-arm: A64: add support for conditional branches Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 11/12] target-arm: A64: add support for 'test and branch' imm Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 12/12] target-arm: A64: add support for compare and branch imm Peter Maydell
2013-12-05 19:37 ` Richard Henderson
2013-12-17 14:45 ` [Qemu-devel] [PATCH v3 00/12] target-arm: A64 decoder, foundation plus branches Peter Maydell
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