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From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Patch Tracking" <patches@linaro.org>,
	"Michael Matz" <matz@suse.de>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Claudio Fontana" <claudio.fontana@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
	"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 01/13] target-arm: A64: add support for conditional select
Date: Sat, 07 Dec 2013 05:44:22 +1300	[thread overview]
Message-ID: <52A1FEE6.9070000@twiddle.net> (raw)
In-Reply-To: <CAFEAcA-3QOHbVsa7epMUBZNq0C5oBNOU6ii5p4kk9O4V7_2=zQ@mail.gmail.com>

On 12/07/2013 01:45 AM, Peter Maydell wrote:
> On 5 December 2013 22:26, Richard Henderson <rth@twiddle.net> wrote:
>> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>>> +    if (cond >= 0x0e) { /* condition "always" */
>>> +        tcg_src = read_cpu_reg(s, rn, sf);
>>> +        tcg_gen_mov_i64(tcg_rd, tcg_src);
>>
>> I wonder if it's worth adding that 0x0[ef] case to the generic condition
>> processing rather than keep replicating it everywhere.
> 
> I think "always true" is a special case anyway because you don't
> want to emit any kind of branching/label logic at all.

Sure, but unlike unconditional branches, which are useful to special-case, one
sort of expects never to see an unconditional conditional move.  Given
TCG_COND_ALWAYS, we can re-use generic logic and have things fall out
relatively easily.

> I had a think about this and I couldn't really come up with a particularly
> nice looking API for it, given the way that movcondi/setcondi/brcondi work.
> The best I could come up with was something like:

The s390 target has an example with DisasCompare and disas_jcc.
The i386 target has another example with CCPrepare and gen_prepare_cc.

The i386 port uses similar flags to ARM, but represents them differently.  I
suppose good ideas could be taken from either port.


> So I definitely think I'd rather postpone this for now, unless you have
> a neat idea that I've missed for making it look nice.

Let's just postpone for now.


r~

  reply	other threads:[~2013-12-06 16:44 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-05 21:51 [Qemu-devel] [PATCH 00/13] target-arm: A64 decoder set 2: misc logic and bit ops Peter Maydell
2013-12-05 21:51 ` [Qemu-devel] [PATCH 01/13] target-arm: A64: add support for conditional select Peter Maydell
2013-12-05 22:26   ` Richard Henderson
2013-12-05 22:31     ` Peter Maydell
2013-12-05 22:40       ` Richard Henderson
2013-12-06 12:45     ` Peter Maydell
2013-12-06 16:44       ` Richard Henderson [this message]
2013-12-06 17:23         ` Peter Maydell
2013-12-05 21:51 ` [Qemu-devel] [PATCH 02/13] target-arm: A64: add support for logical (shifted register) Peter Maydell
2013-12-05 22:39   ` Richard Henderson
2013-12-06  9:36     ` Alex Bennée
2013-12-06 16:49       ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 03/13] target-arm: A64: add support for ADR and ADRP Peter Maydell
2013-12-05 22:41   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 04/13] target-arm: A64: add support for EXTR Peter Maydell
2013-12-05 22:47   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 05/13] target-arm: A64: add support for 2-src data processing and DIV Peter Maydell
2013-12-05 22:51   ` Richard Henderson
2013-12-05 23:09     ` Peter Maydell
2013-12-05 23:13       ` Richard Henderson
2013-12-05 23:21       ` C Fontana
2013-12-05 23:24       ` Eric Blake
2013-12-05 21:51 ` [Qemu-devel] [PATCH 06/13] target-arm: A64: add support for 2-src shift reg insns Peter Maydell
2013-12-05 22:52   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 07/13] target-arm: A64: add support for 1-src data processing and CLZ Peter Maydell
2013-12-05 22:54   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 08/13] target-arm: A64: add support for 1-src RBIT insn Peter Maydell
2013-12-05 22:56   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 09/13] target-arm: A64: add support for 1-src REV insns Peter Maydell
2013-12-05 23:01   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 10/13] target-arm: A64: add support for bitfield insns Peter Maydell
2013-12-05 23:05   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits Peter Maydell
2013-12-05 23:06   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 12/13] target-arm: A64: add support for 1-src CLS insn Peter Maydell
2013-12-05 23:06   ` Richard Henderson
2013-12-05 21:51 ` [Qemu-devel] [PATCH 13/13] target-arm: A64: add support for logical (immediate) insns Peter Maydell
2013-12-05 23:39   ` Richard Henderson

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