From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select
Date: Mon, 09 Dec 2013 09:03:14 -0800 [thread overview]
Message-ID: <52A5F7D2.6060201@twiddle.net> (raw)
In-Reply-To: <1386592654-362-2-git-send-email-peter.maydell@linaro.org>
On 12/09/2013 04:37 AM, Peter Maydell wrote:
> From: Claudio Fontana <claudio.fontana@linaro.org>
>
> This patch adds support for the instruction group "C3.5.6
> Conditional select": CSEL, CSINC, CSINV, CSNEG.
>
> Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
> [PMM: Improved code generated in the nomatch case as per RTH suggestions]
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/translate-a64.c | 67 ++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2013-12-09 17:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 12:37 [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select Peter Maydell
2013-12-09 17:03 ` Richard Henderson [this message]
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 02/13] target-arm: A64: add support for logical (shifted register) Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 03/13] target-arm: A64: add support for ADR and ADRP Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 05/13] target-arm: A64: add support for 2-src data processing and DIV Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 06/13] target-arm: A64: add support for 2-src shift reg insns Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 08/13] target-arm: A64: add support for 1-src RBIT insn Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 09/13] target-arm: A64: add support for 1-src REV insns Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 13/13] target-arm: A64: add support for logical (immediate) insns Peter Maydell
2013-12-17 14:45 ` [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops Peter Maydell
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