From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46027) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vq7H5-0004Rk-VQ for qemu-devel@nongnu.org; Mon, 09 Dec 2013 15:18:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vq7Gx-00034q-HK for qemu-devel@nongnu.org; Mon, 09 Dec 2013 15:17:51 -0500 Received: from mail-pb0-x22e.google.com ([2607:f8b0:400e:c01::22e]:49234) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vq7Gx-00034k-4P for qemu-devel@nongnu.org; Mon, 09 Dec 2013 15:17:43 -0500 Received: by mail-pb0-f46.google.com with SMTP id md12so6065045pbc.33 for ; Mon, 09 Dec 2013 12:17:42 -0800 (PST) Sender: Richard Henderson Message-ID: <52A62562.7040005@twiddle.net> Date: Mon, 09 Dec 2013 12:17:38 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1386612744-1013-1-git-send-email-peter.maydell@linaro.org> <1386612744-1013-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386612744-1013-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/9] target-arm: A64: add support for stp (store pair) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?B?QWxleCBCZW5uw6ll?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 12/09/2013 10:12 AM, Peter Maydell wrote: > +static void do_gpr_st(DisasContext *s, TCGv_i64 source, > + TCGv_i64 tcg_addr, int size) > +{ > + switch (size) { > + case 0: > + tcg_gen_qemu_st8(source, tcg_addr, get_mem_index(s)); > + break; > + case 1: > + tcg_gen_qemu_st16(source, tcg_addr, get_mem_index(s)); > + break; > + case 2: > + tcg_gen_qemu_st32(source, tcg_addr, get_mem_index(s)); > + break; > + case 3: > + tcg_gen_qemu_st64(source, tcg_addr, get_mem_index(s)); > + break; Please use the new ldst entry points. In this case, tcg_gen_qemu_st_i64(source, tcg_addr, get_mem_index(s), MO_TE + size) since size is already log2. > +static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) > +{ > + /* This writes the bottom N bits of a 128 bit wide vector to memory */ > + int freg_offs = offsetof(CPUARMState, vfp.regs[srcidx * 2]); > + TCGv_i64 tmp = tcg_temp_new_i64(); > + > + switch (size) { > + case 0: > + tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs); > + tcg_gen_qemu_st8(tmp, tcg_addr, get_mem_index(s)); > + break; > + case 1: > + tcg_gen_ld16u_i64(tmp, cpu_env, freg_offs); > + tcg_gen_qemu_st16(tmp, tcg_addr, get_mem_index(s)); > + break; > + case 2: > + tcg_gen_ld32u_i64(tmp, cpu_env, freg_offs); > + tcg_gen_qemu_st32(tmp, tcg_addr, get_mem_index(s)); > + break; > + case 3: > + tcg_gen_ld_i64(tmp, cpu_env, freg_offs); > + tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); > + break; > + case 4: > + { > + TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); > + tcg_gen_ld_i64(tmp, cpu_env, freg_offs); > + tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); > + tcg_gen_ld_i64(tmp, cpu_env, freg_offs + sizeof(float64)); > + tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); > + tcg_gen_qemu_st64(tmp, tcg_hiaddr, get_mem_index(s)); > + tcg_temp_free_i64(tcg_hiaddr); > + break; > + } You'll certainly have to continue to special-case the 128-bit store, but the other sizes need not be. > +/* > + * C5.6.177 STP (Store Pair - non vector) > + * C6.3.284 STP (Store Pair of SIMD&FP) > + * > + * 31 30 29 27 26 25 23 22 21 15 14 10 9 5 4 0 > + * +-----+-------+---+-------+--+-----------------------------+ > + * | opc | 1 0 1 | V | index | 0| imm7 | Rt2 | Rn | Rt | > + * +-----+-------+---+-------+--+-------+-------+------+------+ > + * > + * opc: STP 00 -> 32 bit, 10 -> 64 bit > + * STP (SIMD&FP) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit > + * idx: 001 -> post-index, 011 -> pre-index, 010 -> signed off > + * > + * Rt, Rt2 = GPR or SIMD registers to be stored > + * Rn = general purpose register containing address > + * imm7 = signed offset (multiple of 4 or 8 depending on size) > + */ > +static void handle_stp(DisasContext *s, uint32_t insn) > +{ > + int rt = extract32(insn, 0, 5); > + int rn = extract32(insn, 5, 5); > + int rt2 = extract32(insn, 10, 5); > + int64_t offset = sextract32(insn, 15, 7); > + int type = extract32(insn, 23, 2); > + bool is_vector = extract32(insn, 26, 1); > + int opc = extract32(insn, 30, 2); > + > + TCGv_i64 tcg_rt = cpu_reg(s, rt); > + TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); If you're going to combine vector and non-vector STP, then I think it would be cleaner if you didn't load these registers so early, when we're not even sure if we're talking about general registers. > + if (wback) { > + if (postindex) { > + tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); > + } else { > + tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); > + } Perhaps better as tcg_gen_addi_i64(tcg_addr, tcg_addr, (postindex ? offset : 0) - (1 << size)); ? r~