* [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent @ 2013-12-12 23:28 Ben Widawsky 2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky 2013-12-13 1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao 0 siblings, 2 replies; 9+ messages in thread From: Ben Widawsky @ 2013-12-12 23:28 UTC (permalink / raw) To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky I stumbled on to some unimplemented errata. To be honest, I am not really sure of the impact, just that the docs say to do. No w/a name for this one. Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e8cc27c..3259e83 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4167,6 +4167,10 @@ #define GEN7_L3SQCREG4 0xb034 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) +/* GEN8 chicken */ +#define HDC_CHICKEN0 0x7300 +#define HDC_FORCE_NON_COHERENT (1<<4) + /* WaCatErrorRejectionIssue */ #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ac9dd46..7e2a0e9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5279,6 +5279,13 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_READ(CHICKEN_PIPESL_1(i) | DPRS_MASK_VBLANK_SRD)); } + + /* Use Force Non-Coherent whenever executing a 3D context. This is a + * workaround for for a possible hang in the unlikely event a TLB + * invalidation occurs during a PSD flush. + */ + I915_WRITE(HDC_FORCE_NON_COHERENT, + I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); } static void haswell_init_clock_gating(struct drm_device *dev) -- 1.8.5.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] drm/i915/bdw: Implement ff workarounds 2013-12-12 23:28 [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Ben Widawsky @ 2013-12-12 23:28 ` Ben Widawsky 2013-12-13 11:09 ` Damien Lespiau 2013-12-13 20:28 ` Kenneth Graunke 2013-12-13 1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao 1 sibling, 2 replies; 9+ messages in thread From: Ben Widawsky @ 2013-12-12 23:28 UTC (permalink / raw) To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky WaVSRefCountFullforceMissDisable and WaDSRefCountFullforceMissDisable VS is a carry-over from HSW, and DS is likely not used by anyone yet. Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3259e83..f1eece4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1003,6 +1003,7 @@ #define GEN7_FF_THREAD_MODE 0x20a0 #define GEN7_FF_SCHED_MASK 0x0077070 +#define GEN8_FF_DS_REF_CNT_FFME (1 << 19) #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7e2a0e9..424a9d8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5266,14 +5266,14 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); - /* WaSwitchSolVfFArbitrationPriority */ + /* WaSwitchSolVfFArbitrationPriority:bdw */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); - /* WaPsrDPAMaskVBlankInSRD */ + /* WaPsrDPAMaskVBlankInSRD:bdw */ I915_WRITE(CHICKEN_PAR1_1, I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); - /* WaPsrDPRSUnmaskVBlankInSRD */ + /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ for_each_pipe(i) { I915_WRITE(CHICKEN_PIPESL_1(i), I915_READ(CHICKEN_PIPESL_1(i) | @@ -5286,6 +5286,11 @@ static void gen8_init_clock_gating(struct drm_device *dev) */ I915_WRITE(HDC_FORCE_NON_COHERENT, I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); + + /* WaVSRefCountFullforceMissDisable:bdw */ + /* WaDSRefCountFullforceMissDisable:bdw */ + I915_WRITE(GEN7_FF_THREAD_MODE, + I915_READ(GEN7_FF_THREAD_MODE) & ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); } static void haswell_init_clock_gating(struct drm_device *dev) -- 1.8.5.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915/bdw: Implement ff workarounds 2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky @ 2013-12-13 11:09 ` Damien Lespiau 2013-12-13 16:56 ` Daniel Vetter 2013-12-13 20:28 ` Kenneth Graunke 1 sibling, 1 reply; 9+ messages in thread From: Damien Lespiau @ 2013-12-13 11:09 UTC (permalink / raw) To: Ben Widawsky; +Cc: Intel GFX, Ben Widawsky On Thu, Dec 12, 2013 at 03:28:04PM -0800, Ben Widawsky wrote: > WaVSRefCountFullforceMissDisable and > WaDSRefCountFullforceMissDisable > > VS is a carry-over from HSW, and DS is likely not used by anyone yet. > > Cc: Kenneth Graunke <kenneth@whitecape.org> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++--- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3259e83..f1eece4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1003,6 +1003,7 @@ > > #define GEN7_FF_THREAD_MODE 0x20a0 > #define GEN7_FF_SCHED_MASK 0x0077070 > +#define GEN8_FF_DS_REF_CNT_FFME (1 << 19) > #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) > #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) > #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7e2a0e9..424a9d8 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5266,14 +5266,14 @@ static void gen8_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > - /* WaSwitchSolVfFArbitrationPriority */ > + /* WaSwitchSolVfFArbitrationPriority:bdw */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > > - /* WaPsrDPAMaskVBlankInSRD */ > + /* WaPsrDPAMaskVBlankInSRD:bdw */ > I915_WRITE(CHICKEN_PAR1_1, > I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); > > - /* WaPsrDPRSUnmaskVBlankInSRD */ > + /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ > for_each_pipe(i) { > I915_WRITE(CHICKEN_PIPESL_1(i), > I915_READ(CHICKEN_PIPESL_1(i) | > @@ -5286,6 +5286,11 @@ static void gen8_init_clock_gating(struct drm_device *dev) > */ > I915_WRITE(HDC_FORCE_NON_COHERENT, > I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); > + > + /* WaVSRefCountFullforceMissDisable:bdw */ > + /* WaDSRefCountFullforceMissDisable:bdw */ > + I915_WRITE(GEN7_FF_THREAD_MODE, > + I915_READ(GEN7_FF_THREAD_MODE) & ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); > } > > static void haswell_init_clock_gating(struct drm_device *dev) > -- > 1.8.5.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915/bdw: Implement ff workarounds 2013-12-13 11:09 ` Damien Lespiau @ 2013-12-13 16:56 ` Daniel Vetter 0 siblings, 0 replies; 9+ messages in thread From: Daniel Vetter @ 2013-12-13 16:56 UTC (permalink / raw) To: Damien Lespiau; +Cc: Intel GFX, Ben Widawsky, Ben Widawsky On Fri, Dec 13, 2013 at 11:09:58AM +0000, Damien Lespiau wrote: > On Thu, Dec 12, 2013 at 03:28:04PM -0800, Ben Widawsky wrote: > > WaVSRefCountFullforceMissDisable and > > WaDSRefCountFullforceMissDisable > > > > VS is a carry-over from HSW, and DS is likely not used by anyone yet. > > > > Cc: Kenneth Graunke <kenneth@whitecape.org> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++--- > > 2 files changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 3259e83..f1eece4 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1003,6 +1003,7 @@ > > > > #define GEN7_FF_THREAD_MODE 0x20a0 > > #define GEN7_FF_SCHED_MASK 0x0077070 > > +#define GEN8_FF_DS_REF_CNT_FFME (1 << 19) > > #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) > > #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) > > #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 7e2a0e9..424a9d8 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -5266,14 +5266,14 @@ static void gen8_init_clock_gating(struct drm_device *dev) > > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > > > - /* WaSwitchSolVfFArbitrationPriority */ > > + /* WaSwitchSolVfFArbitrationPriority:bdw */ > > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > > > > - /* WaPsrDPAMaskVBlankInSRD */ > > + /* WaPsrDPAMaskVBlankInSRD:bdw */ > > I915_WRITE(CHICKEN_PAR1_1, > > I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); > > > > - /* WaPsrDPRSUnmaskVBlankInSRD */ > > + /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ > > for_each_pipe(i) { > > I915_WRITE(CHICKEN_PIPESL_1(i), > > I915_READ(CHICKEN_PIPESL_1(i) | > > @@ -5286,6 +5286,11 @@ static void gen8_init_clock_gating(struct drm_device *dev) > > */ > > I915_WRITE(HDC_FORCE_NON_COHERENT, > > I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); > > + > > + /* WaVSRefCountFullforceMissDisable:bdw */ > > + /* WaDSRefCountFullforceMissDisable:bdw */ > > + I915_WRITE(GEN7_FF_THREAD_MODE, > > + I915_READ(GEN7_FF_THREAD_MODE) & ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); Even with loads of fugde this is too long. I've broken it. Otherwise both patches applied, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915/bdw: Implement ff workarounds 2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky 2013-12-13 11:09 ` Damien Lespiau @ 2013-12-13 20:28 ` Kenneth Graunke 1 sibling, 0 replies; 9+ messages in thread From: Kenneth Graunke @ 2013-12-13 20:28 UTC (permalink / raw) To: Ben Widawsky, Intel GFX; +Cc: Ben Widawsky On 12/12/2013 03:28 PM, Ben Widawsky wrote: > WaVSRefCountFullforceMissDisable and > WaDSRefCountFullforceMissDisable > > VS is a carry-over from HSW, and DS is likely not used by anyone yet. You're correct that no one uses DS; we don't support GL 4.0's tessellation shaders yet. I was about to comment that the Haswell workaround is missing, but it's just implemented in a different function: gen7_setup_fixed_func_scheduler. Both patches are: Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Too late to get tagged, but still under 24 hours after posting... > > Cc: Kenneth Graunke <kenneth@whitecape.org> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++--- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3259e83..f1eece4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1003,6 +1003,7 @@ > > #define GEN7_FF_THREAD_MODE 0x20a0 > #define GEN7_FF_SCHED_MASK 0x0077070 > +#define GEN8_FF_DS_REF_CNT_FFME (1 << 19) > #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) > #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) > #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7e2a0e9..424a9d8 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5266,14 +5266,14 @@ static void gen8_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > - /* WaSwitchSolVfFArbitrationPriority */ > + /* WaSwitchSolVfFArbitrationPriority:bdw */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > > - /* WaPsrDPAMaskVBlankInSRD */ > + /* WaPsrDPAMaskVBlankInSRD:bdw */ > I915_WRITE(CHICKEN_PAR1_1, > I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); > > - /* WaPsrDPRSUnmaskVBlankInSRD */ > + /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ > for_each_pipe(i) { > I915_WRITE(CHICKEN_PIPESL_1(i), > I915_READ(CHICKEN_PIPESL_1(i) | > @@ -5286,6 +5286,11 @@ static void gen8_init_clock_gating(struct drm_device *dev) > */ > I915_WRITE(HDC_FORCE_NON_COHERENT, > I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); > + > + /* WaVSRefCountFullforceMissDisable:bdw */ > + /* WaDSRefCountFullforceMissDisable:bdw */ > + I915_WRITE(GEN7_FF_THREAD_MODE, > + I915_READ(GEN7_FF_THREAD_MODE) & ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); > } > > static void haswell_init_clock_gating(struct drm_device *dev) > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent 2013-12-12 23:28 [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Ben Widawsky 2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky @ 2013-12-13 1:16 ` Xiang, Haihao 2013-12-13 1:18 ` Ben Widawsky 2013-12-13 1:26 ` [PATCH 1/2] [v2] " Ben Widawsky 1 sibling, 2 replies; 9+ messages in thread From: Xiang, Haihao @ 2013-12-13 1:16 UTC (permalink / raw) To: Ben Widawsky; +Cc: Intel GFX, Ben Widawsky On Thu, 2013-12-12 at 15:28 -0800, Ben Widawsky wrote: > I stumbled on to some unimplemented errata. To be honest, I am not > really sure of the impact, just that the docs say to do. > > No w/a name for this one. > > Cc: Kenneth Graunke <kenneth@whitecape.org> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e8cc27c..3259e83 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4167,6 +4167,10 @@ > #define GEN7_L3SQCREG4 0xb034 > #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > > +/* GEN8 chicken */ > +#define HDC_CHICKEN0 0x7300 > +#define HDC_FORCE_NON_COHERENT (1<<4) > + > /* WaCatErrorRejectionIssue */ > #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 > #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ac9dd46..7e2a0e9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5279,6 +5279,13 @@ static void gen8_init_clock_gating(struct drm_device *dev) > I915_READ(CHICKEN_PIPESL_1(i) | > DPRS_MASK_VBLANK_SRD)); > } > + > + /* Use Force Non-Coherent whenever executing a 3D context. This is a > + * workaround for for a possible hang in the unlikely event a TLB > + * invalidation occurs during a PSD flush. > + */ > + I915_WRITE(HDC_FORCE_NON_COHERENT, It should be HDC_CHICKEN0 instead of HDC_FORCE_NON_COHERENT > + I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); It has a mask bit which should be set for writing > } > > static void haswell_init_clock_gating(struct drm_device *dev) ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent 2013-12-13 1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao @ 2013-12-13 1:18 ` Ben Widawsky 2013-12-13 1:26 ` [PATCH 1/2] [v2] " Ben Widawsky 1 sibling, 0 replies; 9+ messages in thread From: Ben Widawsky @ 2013-12-13 1:18 UTC (permalink / raw) To: Xiang, Haihao; +Cc: Intel GFX, Ben Widawsky On Fri, Dec 13, 2013 at 09:16:47AM +0800, Xiang, Haihao wrote: > On Thu, 2013-12-12 at 15:28 -0800, Ben Widawsky wrote: > > I stumbled on to some unimplemented errata. To be honest, I am not > > really sure of the impact, just that the docs say to do. > > > > No w/a name for this one. > > > > Cc: Kenneth Graunke <kenneth@whitecape.org> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ > > 2 files changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index e8cc27c..3259e83 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4167,6 +4167,10 @@ > > #define GEN7_L3SQCREG4 0xb034 > > #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > > > > +/* GEN8 chicken */ > > +#define HDC_CHICKEN0 0x7300 > > +#define HDC_FORCE_NON_COHERENT (1<<4) > > + > > /* WaCatErrorRejectionIssue */ > > #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 > > #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index ac9dd46..7e2a0e9 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -5279,6 +5279,13 @@ static void gen8_init_clock_gating(struct drm_device *dev) > > I915_READ(CHICKEN_PIPESL_1(i) | > > DPRS_MASK_VBLANK_SRD)); > > } > > + > > + /* Use Force Non-Coherent whenever executing a 3D context. This is a > > + * workaround for for a possible hang in the unlikely event a TLB > > + * invalidation occurs during a PSD flush. > > + */ > > + I915_WRITE(HDC_FORCE_NON_COHERENT, > > It should be HDC_CHICKEN0 instead of HDC_FORCE_NON_COHERENT > > > + I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); > > It has a mask bit which should be set for writing > > > } > > > > static void haswell_init_clock_gating(struct drm_device *dev) > > Damn, sorry - I sent the wrong patch. Thanks for catching it. -- Ben Widawsky, Intel Open Source Technology Center ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] [v2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent 2013-12-13 1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao 2013-12-13 1:18 ` Ben Widawsky @ 2013-12-13 1:26 ` Ben Widawsky 2013-12-13 10:50 ` Damien Lespiau 1 sibling, 1 reply; 9+ messages in thread From: Ben Widawsky @ 2013-12-13 1:26 UTC (permalink / raw) To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky I stumbled on to some unimplemented errata. To be honest, I am not really sure of the impact, just that the docs say to do. No w/a name for this one. v2: v1 was a stale thing which should have never seen the light of day. (Haihao) Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e8cc27c..3259e83 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4167,6 +4167,10 @@ #define GEN7_L3SQCREG4 0xb034 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) +/* GEN8 chicken */ +#define HDC_CHICKEN0 0x7300 +#define HDC_FORCE_NON_COHERENT (1<<4) + /* WaCatErrorRejectionIssue */ #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ac9dd46..0665e37 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5279,6 +5279,14 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_READ(CHICKEN_PIPESL_1(i) | DPRS_MASK_VBLANK_SRD)); } + + /* Use Force Non-Coherent whenever executing a 3D context. This is a + * workaround for for a possible hang in the unlikely event a TLB + * invalidation occurs during a PSD flush. + */ + I915_WRITE(HDC_CHICKEN0, + I915_READ(HDC_CHICKEN0) | + _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); } static void haswell_init_clock_gating(struct drm_device *dev) -- 1.8.4.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] [v2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent 2013-12-13 1:26 ` [PATCH 1/2] [v2] " Ben Widawsky @ 2013-12-13 10:50 ` Damien Lespiau 0 siblings, 0 replies; 9+ messages in thread From: Damien Lespiau @ 2013-12-13 10:50 UTC (permalink / raw) To: Ben Widawsky; +Cc: Intel GFX, Ben Widawsky On Thu, Dec 12, 2013 at 05:26:03PM -0800, Ben Widawsky wrote: > I stumbled on to some unimplemented errata. To be honest, I am not > really sure of the impact, just that the docs say to do. > > No w/a name for this one. WaForceEnableNonCoherent looks like a good candidate. > v2: v1 was a stale thing which should have never seen the light of day. > (Haihao) > > Cc: Kenneth Graunke <kenneth@whitecape.org> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e8cc27c..3259e83 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4167,6 +4167,10 @@ > #define GEN7_L3SQCREG4 0xb034 > #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > > +/* GEN8 chicken */ > +#define HDC_CHICKEN0 0x7300 > +#define HDC_FORCE_NON_COHERENT (1<<4) > + > /* WaCatErrorRejectionIssue */ > #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 > #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ac9dd46..0665e37 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5279,6 +5279,14 @@ static void gen8_init_clock_gating(struct drm_device *dev) > I915_READ(CHICKEN_PIPESL_1(i) | > DPRS_MASK_VBLANK_SRD)); > } > + > + /* Use Force Non-Coherent whenever executing a 3D context. This is a > + * workaround for for a possible hang in the unlikely event a TLB > + * invalidation occurs during a PSD flush. > + */ > + I915_WRITE(HDC_CHICKEN0, > + I915_READ(HDC_CHICKEN0) | > + _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); > } > > static void haswell_init_clock_gating(struct drm_device *dev) > -- > 1.8.4.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-12-13 20:25 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-12-12 23:28 [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Ben Widawsky 2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky 2013-12-13 11:09 ` Damien Lespiau 2013-12-13 16:56 ` Daniel Vetter 2013-12-13 20:28 ` Kenneth Graunke 2013-12-13 1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao 2013-12-13 1:18 ` Ben Widawsky 2013-12-13 1:26 ` [PATCH 1/2] [v2] " Ben Widawsky 2013-12-13 10:50 ` Damien Lespiau
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