From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VsHwW-00020B-3l for qemu-devel@nongnu.org; Sun, 15 Dec 2013 15:05:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VsHwR-0000h2-5S for qemu-devel@nongnu.org; Sun, 15 Dec 2013 15:05:36 -0500 Received: from cantor2.suse.de ([195.135.220.15]:53489 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VsHwQ-0000gy-VM for qemu-devel@nongnu.org; Sun, 15 Dec 2013 15:05:31 -0500 Message-ID: <52AE0B85.5080200@suse.de> Date: Sun, 15 Dec 2013 21:05:25 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <87vbyqn4s3.fsf@moxielogic.com> <87situl1ou.fsf@moxielogic.com> In-Reply-To: <87situl1ou.fsf@moxielogic.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target-moxie: Add moxie Marin SoC support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Green Cc: Peter Maydell , Peter Crosthwaite , Antony Pavlov , liguang , "qemu-devel@nongnu.org Developers" Hi, Am 15.12.2013 13:48, schrieb Anthony Green: > Peter Crosthwaite writes: >> On Sun, Dec 15, 2013 at 1:59 PM, Anthony Green = wrote: >>> diff --git a/hw/moxie/marin.c b/hw/moxie/marin.c >>> new file mode 100644 >>> index 0000000..0a998e4 >>> --- /dev/null >>> +++ b/hw/moxie/marin.c >>> @@ -0,0 +1,167 @@ >>> +/* >>> + * QEMU/marin SoC emulation >>> + * >>> + * Emulates the FPGA-hosted Marin SoC [...] >>> +static QEMUMachine marin_machine =3D { >>> + .name =3D "marin", >>> + .desc =3D "Marin SoC", >> >> So SoCs should generally be implemented on two levels. There is the >> SoC device, which contains the devices that are on the SoC chip, then >> the board level instantiates the SoC. This looks like a flat >> board-and-SoC in one (on board level). Your deisgn is trivial so far >> (and good for a first series), but long term what is the organsation? >> Is this going towards a particular board emulation? Have a look at >> Liguangs Allwinner series (and some of the early review comments) for >> a discussion on this topic: >> >> http://lists.gnu.org/archive/html/qemu-devel/2013-11/msg03940.html >> >> As a starting point, can you tell us what is and isn't hosted on the >> FPGA in this board model? That might be the best way to split this. >=20 > The Marin SoC currently runs on two boards: the Nexys3 (Xilinx) and DE-= 2 > (Altera). They are pretty much identical from the software side of > things. Marin currently provides the UART, PIC, 7 segment display and > timer devices, as well as various memory controllers. There's no usefu= l > distinction between SoC and board at this time. I'd like to keep it > simple as per my patch rather than try to factor them out prematurely. I thought I've seen a number of odd embedded systems already, but I'm having trouble understanding your combination of SoC and FPGA: Xilinx and Altera both have SoCs combining a Cortex-A9 with an FPGA. But your reference to Xilinx and Altera boards rather sounds as if Moxie is used as a soft-core processor on the FPGA? In that case the term "SoC" would be really confusing to me... Can you clarify or aid with some links? Regards, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg