From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vtkaz-0000Mv-Lv for qemu-devel@nongnu.org; Thu, 19 Dec 2013 15:53:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vtkar-0008WA-90 for qemu-devel@nongnu.org; Thu, 19 Dec 2013 15:53:25 -0500 Received: from mail-qa0-x236.google.com ([2607:f8b0:400d:c00::236]:37115) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vtkar-0008W6-4q for qemu-devel@nongnu.org; Thu, 19 Dec 2013 15:53:17 -0500 Received: by mail-qa0-f54.google.com with SMTP id f11so1940711qae.20 for ; Thu, 19 Dec 2013 12:53:16 -0800 (PST) Sender: Richard Henderson Message-ID: <52B35CB8.9000508@twiddle.net> Date: Thu, 19 Dec 2013 12:53:12 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1387293144-11554-1-git-send-email-peter.maydell@linaro.org> <1387293144-11554-16-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1387293144-11554-16-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 15/21] target-arm: Widen thread-local register state fields to 64 bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?ISO-8859-1?Q?Alex_Benn=E9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 12/17/2013 07:12 AM, Peter Maydell wrote: > - uint32_t c13_tls1; /* User RW Thread register. */ > - uint32_t c13_tls2; /* User RO Thread register. */ > - uint32_t c13_tls3; /* Privileged Thread register. */ > + uint64_t tpidr_el0; /* User RW Thread register. */ > + uint64_t tpidrro_el0; /* User RO Thread register. */ > + uint64_t tpidr_el1; /* Privileged Thread register. */ Not target_ulong, continuing to use 32bit slot for pure AA32? r~