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Date: Thu, 19 Dec 2013 13:09:14 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 15/21] target-arm: Widen thread-local
 register state fields to 64 bits
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, Christoffer Dall <christoffer.dall@linaro.org>

On 12/19/2013 01:04 PM, Peter Maydell wrote:
> On 19 December 2013 20:53, Richard Henderson <rth@twiddle.net> wrote:
>> On 12/17/2013 07:12 AM, Peter Maydell wrote:
>>> -        uint32_t c13_tls1; /* User RW Thread register.  */
>>> -        uint32_t c13_tls2; /* User RO Thread register.  */
>>> -        uint32_t c13_tls3; /* Privileged Thread register.  */
>>> +        uint64_t tpidr_el0; /* User RW Thread register.  */
>>> +        uint64_t tpidrro_el0; /* User RO Thread register.  */
>>> +        uint64_t tpidr_el1; /* Privileged Thread register.  */
>>
>> Not target_ulong, continuing to use 32bit slot for pure AA32?
> 
> It would only be a 32 bit slot for the 32 bit cores in qemu-arm;
> the same cores in qemu-aarch64 would be 64 bits. I think
> I'd rather have the consistency (and the ability to migrate
> between a qemu-arm cortex-a9 and a qemu-aarch64 cortex-a9
> doesn't hurt).

Fair enough.

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~