From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vu1Dy-0004pX-LO for qemu-devel@nongnu.org; Fri, 20 Dec 2013 09:38:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vu1Dq-0004BS-Sn for qemu-devel@nongnu.org; Fri, 20 Dec 2013 09:38:46 -0500 Received: from mailout4.w1.samsung.com ([210.118.77.14]:48087) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vu1Dq-0004BM-MQ for qemu-devel@nongnu.org; Fri, 20 Dec 2013 09:38:38 -0500 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MY4006EU0OCUN50@mailout4.w1.samsung.com> for qemu-devel@nongnu.org; Fri, 20 Dec 2013 14:38:36 +0000 (GMT) Message-id: <52B4566B.9010608@samsung.com> Date: Fri, 20 Dec 2013 18:38:35 +0400 From: Fedorov Sergey MIME-version: 1.0 References: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com> <1386060535-15908-19-git-send-email-s.fedorov@samsung.com> <52B29FE5.40705@samsung.com> <52B4504C.7000707@samsung.com> In-reply-to: Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Johannes Winter , Peter Crosthwaite , a.basov@samsung.com, "qemu-devel@nongnu.org Developers" On 12/20/2013 06:33 PM, Peter Maydell wrote: > On 20 December 2013 14:12, Fedorov Sergey wrote: >> I've briefly looked at the v8 ARM ARM. As I can see there is no banked >> system control registers in AArch64. Seems the concept is changed to provide >> separate registers for each meaningful execution level. Please, correct me >> if I am wrong. > Yes, I think this is generally correct. > >> So I think there shouldn't be "active" and "banked" fields for banked >> AArch32 CP15 registers as in my patch. Seems it is worth to use AArch64 view >> of system control registers as a basis. That means there would be separate S >> and NS register fields in CPU state structure that will me mapped to >> separate AArch64 registers. ARMCPRegInfo structure would have additional >> field holding NS register state filed offset for AArch32 banked registers. > This sounds like it could work, though there are some wrinkles for > registers with readfns/writefns -- do we have extra s vs ns read/write > functions, or just one set of functions which has to look in env->ns to > figure out whether to use the S or NS version? I think if most read/write functions do the same work for both S/NS versions then this code should not be duplicated. > >> Which branch in https://git.linaro.org/people/peter.maydell/qemu-arm.git >> repository holds the most actual A64 support? > It's still a work in progress so it depends what you want. > a64-third-fourth-set is the last set of patches that went out for > review, and should generally work for integer instructions. > a64-working is my work-in-progress branch so it will have the > most recent versions of everything, but it rebases frequently > and is liable to occasionally be broken... Thanks. > > thanks > -- PMM > -- Best regards, Sergey Fedorov