From: Fedorov Sergey <s.fedorov@samsung.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Johannes Winter <johannes.winter@iaik.tugraz.at>,
Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
a.basov@samsung.com,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers
Date: Mon, 23 Dec 2013 11:43:10 +0400 [thread overview]
Message-ID: <52B7E98E.1000406@samsung.com> (raw)
In-Reply-To: <CAFEAcA8CJw1Lj4ZaG=H3anHUUZ3nsn7ShG7OR3SDbuNiCt-kMQ@mail.gmail.com>
On 12/20/2013 06:33 PM, Peter Maydell wrote:
> This sounds like it could work, though there are some wrinkles for
> registers with readfns/writefns -- do we have extra s vs ns read/write
> functions, or just one set of functions which has to look in env->ns to
> figure out whether to use the S or NS version?
What about defining a separate ARMCPRegInfo for each banked AArch32
system register? I think it would be close to AArch64 concept. It would
allow to use separate read/write handlers if necessary or reuse the same
handlers otherwise. When the handlers is not used, the translation code
would simply lookup the ARMCPRegInfo for corresponding secure state and
use the field offset.
Best regards,
Sergey Fedorov
next prev parent reply other threads:[~2013-12-23 7:43 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-03 8:48 [Qemu-devel] [RFC PATCH 00/21] target-arm: add CPU core TrustZone support Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 01/21] target-arm: add TrustZone CPU feature Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 02/21] target-arm: move SCR & VBAR into TrustZone register list Sergey Fedorov
2013-12-19 3:12 ` Peter Crosthwaite
2013-12-19 6:23 ` Fedorov Sergey
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 03/21] target-arm: adjust TTBCR for TrustZone feature Sergey Fedorov
2013-12-03 12:15 ` Peter Crosthwaite
2013-12-04 9:50 ` Fedorov Sergey
2013-12-04 10:52 ` Peter Crosthwaite
2013-12-19 3:18 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 04/21] target-arm: preserve RAO/WI bits of ARMv7 SCTLR Sergey Fedorov
2013-12-03 12:17 ` Peter Crosthwaite
2013-12-04 9:55 ` Fedorov Sergey
2013-12-19 3:19 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode Sergey Fedorov
2013-12-03 12:20 ` Peter Crosthwaite
2013-12-03 12:51 ` Peter Maydell
2013-12-04 10:01 ` Fedorov Sergey
2013-12-04 10:58 ` Peter Crosthwaite
2013-12-04 11:18 ` Peter Maydell
2013-12-04 12:33 ` Fedorov Sergey
2013-12-04 12:35 ` Peter Maydell
2013-12-19 3:26 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 06/21] target-arm: add arm_is_secure() helper Sergey Fedorov
2013-12-19 3:31 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 07/21] target-arm: reject switching to monitor mode from non-secure state Sergey Fedorov
2013-12-19 3:44 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 08/21] target-arm: adjust arm_current_pl() for TrustZone Sergey Fedorov
2013-12-03 12:23 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 09/21] target-arm: adjust SCR CP15 register access rights Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 10/21] target-arm: add non-secure Translation Block flag Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 11/21] target-arm: implement CPACR register logic Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 12/21] target-arm: add NSACR support Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 13/21] target-arm: add SDER definition Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 14/21] target-arm: split TLB for secure state Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 15/21] target-arm: add banked coprocessor register type Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 16/21] target-arm: convert appropriate coprocessor registers to banked type Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 17/21] target-arm: use c13_context field for CONTEXTIDR Sergey Fedorov
2013-12-19 4:31 ` Peter Crosthwaite
2013-12-19 6:29 ` Fedorov Sergey
2013-12-19 6:32 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers Sergey Fedorov
2013-12-19 4:37 ` Peter Crosthwaite
2013-12-19 7:27 ` Fedorov Sergey
2013-12-19 11:38 ` Peter Maydell
2013-12-19 12:44 ` Peter Crosthwaite
2013-12-19 13:39 ` Fedorov Sergey
2013-12-19 14:01 ` Peter Crosthwaite
2013-12-19 14:09 ` Peter Maydell
2013-12-20 14:12 ` Fedorov Sergey
2013-12-20 14:33 ` Peter Maydell
2013-12-20 14:38 ` Fedorov Sergey
2013-12-20 16:18 ` Fedorov Sergey
2013-12-22 1:08 ` Peter Crosthwaite
2013-12-22 7:59 ` Peter Maydell
2013-12-23 7:28 ` Fedorov Sergey
2013-12-23 7:43 ` Fedorov Sergey [this message]
2013-12-23 9:05 ` Peter Maydell
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 19/21] target-arm: add MVBAR support Sergey Fedorov
2013-12-19 4:41 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 20/21] target-arm: implement SMC instruction Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 21/21] target-arm: implement IRQ/FIQ routing to Monitor mode Sergey Fedorov
2013-12-04 10:08 ` [Qemu-devel] [RFC PATCH 00/21] target-arm: add CPU core TrustZone support Fedorov Sergey
2013-12-04 11:10 ` Peter Crosthwaite
2013-12-04 11:13 ` Peter Maydell
2013-12-04 12:48 ` Fedorov Sergey
2013-12-19 4:56 ` Peter Crosthwaite
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