From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvD25-0004na-7W for qemu-devel@nongnu.org; Mon, 23 Dec 2013 16:27:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvD20-0003sg-Fc for qemu-devel@nongnu.org; Mon, 23 Dec 2013 16:27:25 -0500 Received: from mail-pd0-x236.google.com ([2607:f8b0:400e:c02::236]:47330) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvD20-0003pn-8l for qemu-devel@nongnu.org; Mon, 23 Dec 2013 16:27:20 -0500 Received: by mail-pd0-f182.google.com with SMTP id v10so5592523pde.27 for ; Mon, 23 Dec 2013 13:27:19 -0800 (PST) Sender: Richard Henderson Message-ID: <52B8AAB3.5050400@twiddle.net> Date: Mon, 23 Dec 2013 13:27:15 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1387752607-23755-1-git-send-email-peter.maydell@linaro.org> <1387752607-23755-21-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1387752607-23755-21-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 20/25] target-arm: Widen exclusive-access support struct fields to 64 bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?ISO-8859-1?Q?Alex_Benn=E9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall On 12/22/2013 02:50 PM, Peter Maydell wrote: > In preparation for adding support for A64 load/store exclusive instructions, > widen the fields in the CPU state struct that deal with address and data values > for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32 > exclusive accesses will be generally separate there are some odd theoretical > corner cases (eg you should be able to do the exclusive load in AArch32, take > an exception to AArch64 and successfully do the store exclusive there), and it's > also easier to reason about. > > The changes in semantics for the variables are: > exclusive_addr -> extended to 64 bits; -1ULL for "monitor lost", > otherwise always < 2^32 for AArch32 > exclusive_val -> extended to 64 bits. 64 bit exclusives in AArch32 now > use the high half of exclusive_val instead of a separate exclusive_high > exclusive_high -> is no longer used in AArch32; extended to 64 bits as > it will be needed for AArch64's pair-of-64-bit-values exclusives. > exclusive_test -> extended to 64 bits, as it is an address. Since this is > a linux-user-only field, in arm-linux-user it will always have the top > 32 bits zero. > exclusive_info -> stays 32 bits, as it is neither data nor address, but > simply holds register indexes etc. AArch64 will be able to fit all its > information into 32 bits as well. > > Note that the refactoring of gen_store_exclusive() coincidentally fixes > a minor bug where ldrexd would incorrectly update the first CPU register > even if the load for the second register faulted. > > Signed-off-by: Peter Maydell > --- Reviewed-by: Richard Henderson r~