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Subject: Re: [Qemu-devel] [PATCH 02/10] target-arm: A64: Fix vector register
 access on bigendian hosts
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 12/28/2013 01:49 PM, Peter Maydell wrote:
>      if (size < 4) {
>          switch (size) {
>          case 0:
> -            tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs);
> +            tcg_gen_ld8u_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_8));
>              break;
>          case 1:
> -            tcg_gen_ld16u_i64(tmp, cpu_env, freg_offs);
> +            tcg_gen_ld16u_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_16));
>              break;
>          case 2:
> -            tcg_gen_ld32u_i64(tmp, cpu_env, freg_offs);
> +            tcg_gen_ld32u_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_32));
>              break;
>          case 3:
> -            tcg_gen_ld_i64(tmp, cpu_env, freg_offs);
> +            tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_64));
>              break;
>          }
>          tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size);

It occurs to me to wonder whether it wouldn't just be better to load the whole
64-bit quantity and store the piece we need, ignoring the entire host-endian issue.

I agree with the fp_reg_hi_offset helper, I just wonder if we ought not just
have a one-argument fp_reg_lo_offset helper instead of the sized one you introduce.


r~