Re: [Qemu-devel] [PATCH v2 02/10] target-arm: A64: Fix vector register access on bigendian hosts

[Richard Henderson <rth@twiddle.net>]

On 12/30/2013 08:34 AM, Peter Maydell wrote:
> The A64 128 bit vector registers are stored as a pair of
> uint64_t values in the register array. This means that if
> we're directly loading or storing a value of size less than
> 64 bits we must adjust the offset appropriately to account
> for whether the host is bigendian or not. Provide utility
> functions to abstract away the offsetof() calculations for
> the FP registers.
> 
> For do_fp_st() we can sidestep most of the issues for 64 bit
> and smaller reg-to-mem transfers by always doing a 64 bit
> load from the register and writing just the piece we need
> to memory.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Didn't spot this bug until I started reviewing the FP related
> patches (the code also I think is cleaner without offsetof()
> scattered everywhere).
> ---
>  target-arm/translate-a64.c | 69 +++++++++++++++++++++++-----------------------
>  1 file changed, 35 insertions(+), 34 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~