[U-Boot] [PATCH][v2] powerpc/t1040qds: Update DDR initialization related settings

[York Sun <yorksun@freescale.com>]

On 12/16/2013 09:42 PM, Priyanka Jain wrote:
> Update following DDR related settings for T1040QDS
> -Correct number of chip selects to two as t1040qds supports
>  two Chip selects.
> -Update board_specific_parameters udimm structure with settings
>  derived via calibration.
> -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
>  read at 400KHz.
> 
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> ---
>  Changes for v2:
> 	Reduced I2C speed to 50KHz.
> 
>  board/freescale/t1040qds/ddr.h |   22 ++++++++++++----------
>  include/configs/T1040QDS.h     |    6 +++---
>  2 files changed, 15 insertions(+), 13 deletions(-)
> 
> diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
> index 8ee206e..afa72af 100644
> --- a/board/freescale/t1040qds/ddr.h
> +++ b/board/freescale/t1040qds/ddr.h
> @@ -31,16 +31,18 @@ static const struct board_specific_parameters udimm0[] = {
>  	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
>  	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
>  	 */
> -	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
> -	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
> -	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
> -	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
> -	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
> -	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
> -	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
> -	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
> -	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
> -	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
> +	{2,  833,  4, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
> +	{2,  833,  0, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
> +	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
> +	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
> +	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
> +	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
> +	{1,  833,  4, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
> +	{1,  833,  0, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
> +	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
> +	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
> +	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
> +	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
>  	{}
>  };

Looks you are updating timing for all speeds. Can you add to commit message
about what DIMMs and speeds have you tested?

York