From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] board/t1040qds: Relax IFC FPGA timings
Date: Thu, 2 Jan 2014 15:43:59 -0800 [thread overview]
Message-ID: <52C5F9BF.8050707@freescale.com> (raw)
In-Reply-To: <1386830341-25526-1-git-send-email-prabhakar@freescale.com>
On 12/11/2013 10:39 PM, Prabhakar Kushwaha wrote:
> Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
> is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
> freqencies.
>
> So, Increase TCH as 0x8 i.e. 8 ip_clk.
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
prev parent reply other threads:[~2014-01-02 23:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-12 6:39 [U-Boot] [PATCH] board/t1040qds: Relax IFC FPGA timings Prabhakar Kushwaha
2014-01-02 23:43 ` York Sun [this message]
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