From: ben.dooks@codethink.co.uk (Ben Dooks)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] ARM: dcache: select DCACHE_WORD_ACCESS for big-endian CPUs
Date: Mon, 06 Jan 2014 15:45:28 +0000 [thread overview]
Message-ID: <52CACF98.6010300@codethink.co.uk> (raw)
In-Reply-To: <1387282577-2753-1-git-send-email-will.deacon@arm.com>
On 17/12/13 12:16, Will Deacon wrote:
> With commit 11ec50caedb5 ("word-at-a-time: provide generic big-endian
> zero_bytemask implementation"), the asm-generic word-at-a-time code now
> provides a zero_bytemask implementation, allowing us to make use of
> DCACHE_WORD_ACCESS on big-endian CPUs, providing our
> load_unaligned_zeropad function is endianness-clean.
>
> This patch reworks the load_unaligned_zeropad fixup code to work for
> both big- and little-endian CPUs, then removes the !CPU_BIG_ENDIAN check
> when selecting DCACHE_WORD_ACCESS.
> @@ -73,7 +77,11 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
> " bic %2, %2, #0x3\n"
> " ldr %0, [%2]\n"
> " lsl %1, %1, #0x3\n"
> +#ifndef __ARMEB__
> " lsr %0, %0, %1\n"
> +#else
> + " lsl %0, %0, %1\n"
> +#endif
IIRC we have ARM_BE() and ARM_LE() helpers for this
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
prev parent reply other threads:[~2014-01-06 15:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-17 12:16 [PATCH 1/2] ARM: dcache: select DCACHE_WORD_ACCESS for big-endian CPUs Will Deacon
2013-12-17 12:16 ` [PATCH 2/2] ARM: kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS for CPUv6+ && MMU Will Deacon
2013-12-17 20:34 ` Nicolas Pitre
2014-01-06 14:58 ` Will Deacon
2014-01-06 15:17 ` Nicolas Pitre
2013-12-17 20:27 ` [PATCH 1/2] ARM: dcache: select DCACHE_WORD_ACCESS for big-endian CPUs Nicolas Pitre
2014-01-06 15:45 ` Ben Dooks [this message]
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