Re: [Xenomai] Altera Cyclone V

[Charles Steinkuehler <charles@steinkuehler.net>]

On 1/7/2014 1:52 PM, Lowell Gilbert wrote:
> Hi. 
> 
> I'm starting out trying to get Xenomai running on the ARM cores in the
> "golden reference design" for the Cyclone V SOC from Altera. So far, I'm
> still working on getting a kernel booting with the ipipe support, and I
> could use a hand. If anyone's already worked with this system, or if I
> definitely can't get under 10-microsecond latency with core affinity
> keeping my second core clear of non-real-time processing, I'd appreciate
> a word.
> 
> I'm trying to do this on a 3.10 Linux kernel, because going back much
> further will give me problems with backporting some of the peripheral
> support. I may try 3.8 to see what happens, but I really can't go any
> earlier than 3.6 in any case.

I'd follow Gilles' advice for tracking down issues.  I'm working with
this SoC for my day job, and Xenomai on the A8 (TI AM3359 on a
BeagleBone) for my 3D printing hobby.  I design hardware and can't be
much help with the hard-core kernel coding, but I have a couple of dev
boards and am willing to do some compiling and testing if it would help.

If you're trying to stay under 10 uS latency, you may need to
instantiate a soft core CPU of some sort in the FPGA fabric.  The ARM A
series cores aren't really designed for low IRQ latency, but I haven't
seen numbers from a dual-core A9 part yet.  The single-core A8 on the
BeagleBone is good for about 25 uS typical and 80 uS or so worst case
latency.  I'm sure the dual-core A9 will be better, but you're needing
almost an order of magnitude improvement which seems unlikely (but
perhaps not impossible).

-- 
Charles Steinkuehler
charles@steinkuehler.net

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