From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from service87.mimecast.com (service87.mimecast.com [91.220.42.44]) by ozlabs.org (Postfix) with ESMTP id 66ACE2C007C for ; Fri, 10 Jan 2014 06:34:58 +1100 (EST) Message-ID: <52CEF9E7.4070706@arm.com> Date: Thu, 09 Jan 2014 19:35:03 +0000 From: Sudeep Holla MIME-Version: 1.0 To: Russell King - ARM Linux Subject: Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information References: <1389209168-17189-1-git-send-email-sudeep.holla@arm.com> <1389209168-17189-3-git-send-email-sudeep.holla@arm.com> <20140108205754.GN27432@n2100.arm.linux.org.uk> In-Reply-To: <20140108205754.GN27432@n2100.arm.linux.org.uk> Content-Type: text/plain; charset=WINDOWS-1252 Cc: "devicetree@vger.kernel.org" , Ashok Raj , Rob Herring , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , Greg Kroah-Hartman , Sudeep.Holla@arm.com, "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 08/01/14 20:57, Russell King - ARM Linux wrote: > On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote: >> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */ >> + >> +#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */ >> +#define CTR_CTYPE_SHIFT=09=0924 >> +#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT) >> + >> +static inline unsigned int get_ctr(void) >> +{ >> +=09unsigned int ctr; >> +=09asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=3Dr" (ctr)); >> +=09return ctr; >> +} >> + >> +static enum cache_type get_cache_type(int level) >> +{ >> +=09if (level > MAX_CACHE_LEVEL) >> +=09=09return CACHE_TYPE_NOCACHE; >> +=09return get_ctr() & CTR_CTYPE_MASK ? >> +=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; >=20 > So, what do we do for CPUs that don't implement the CTR? Just return > random rubbish based on decoding the CPU Identity register as if it > were the cache type register? >=20 I assume you referring to some particular CPUs which don't implement this. I could not find it as optional or IMPLEMENTATION defined in ARM ARM. I might be missing to find it or there may be exceptions. Can you please provide more information on that ? Regards, Sudeep From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sudeep.Holla@arm.com (Sudeep Holla) Date: Thu, 09 Jan 2014 19:35:03 +0000 Subject: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information In-Reply-To: <20140108205754.GN27432@n2100.arm.linux.org.uk> References: <1389209168-17189-1-git-send-email-sudeep.holla@arm.com> <1389209168-17189-3-git-send-email-sudeep.holla@arm.com> <20140108205754.GN27432@n2100.arm.linux.org.uk> Message-ID: <52CEF9E7.4070706@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 08/01/14 20:57, Russell King - ARM Linux wrote: > On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote: >> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */ >> + >> +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */ >> +#define CTR_CTYPE_SHIFT 24 >> +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT) >> + >> +static inline unsigned int get_ctr(void) >> +{ >> + unsigned int ctr; >> + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); >> + return ctr; >> +} >> + >> +static enum cache_type get_cache_type(int level) >> +{ >> + if (level > MAX_CACHE_LEVEL) >> + return CACHE_TYPE_NOCACHE; >> + return get_ctr() & CTR_CTYPE_MASK ? >> + CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; > > So, what do we do for CPUs that don't implement the CTR? Just return > random rubbish based on decoding the CPU Identity register as if it > were the cache type register? > I assume you referring to some particular CPUs which don't implement this. I could not find it as optional or IMPLEMENTATION defined in ARM ARM. I might be missing to find it or there may be exceptions. Can you please provide more information on that ? Regards, Sudeep From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sudeep Holla Subject: Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information Date: Thu, 09 Jan 2014 19:35:03 +0000 Message-ID: <52CEF9E7.4070706@arm.com> References: <1389209168-17189-1-git-send-email-sudeep.holla@arm.com> <1389209168-17189-3-git-send-email-sudeep.holla@arm.com> <20140108205754.GN27432@n2100.arm.linux.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <20140108205754.GN27432-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Russell King - ARM Linux Cc: Sudeep.Holla-5wv7dgnIgG8@public.gmane.org, "x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Rob Herring , Benjamin Herrenschmidt , Greg Kroah-Hartman , Ashok Raj List-Id: devicetree@vger.kernel.org On 08/01/14 20:57, Russell King - ARM Linux wrote: > On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote: >> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */ >> + >> +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */ >> +#define CTR_CTYPE_SHIFT 24 >> +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT) >> + >> +static inline unsigned int get_ctr(void) >> +{ >> + unsigned int ctr; >> + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); >> + return ctr; >> +} >> + >> +static enum cache_type get_cache_type(int level) >> +{ >> + if (level > MAX_CACHE_LEVEL) >> + return CACHE_TYPE_NOCACHE; >> + return get_ctr() & CTR_CTYPE_MASK ? >> + CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; > > So, what do we do for CPUs that don't implement the CTR? Just return > random rubbish based on decoding the CPU Identity register as if it > were the cache type register? > I assume you referring to some particular CPUs which don't implement this. I could not find it as optional or IMPLEMENTATION defined in ARM ARM. I might be missing to find it or there may be exceptions. Can you please provide more information on that ? Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756764AbaAITfF (ORCPT ); Thu, 9 Jan 2014 14:35:05 -0500 Received: from service87.mimecast.com ([91.220.42.44]:39086 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752543AbaAITe6 convert rfc822-to-8bit (ORCPT ); Thu, 9 Jan 2014 14:34:58 -0500 Message-ID: <52CEF9E7.4070706@arm.com> Date: Thu, 09 Jan 2014 19:35:03 +0000 From: Sudeep Holla User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 To: Russell King - ARM Linux CC: Sudeep.Holla@arm.com, "x86@kernel.org" , "linuxppc-dev@lists.ozlabs.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Rob Herring , Benjamin Herrenschmidt , Greg Kroah-Hartman , Ashok Raj Subject: Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information References: <1389209168-17189-1-git-send-email-sudeep.holla@arm.com> <1389209168-17189-3-git-send-email-sudeep.holla@arm.com> <20140108205754.GN27432@n2100.arm.linux.org.uk> In-Reply-To: <20140108205754.GN27432@n2100.arm.linux.org.uk> X-OriginalArrivalTime: 09 Jan 2014 19:34:55.0845 (UTC) FILETIME=[E00D0950:01CF0D71] X-MC-Unique: 114010919345600201 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/01/14 20:57, Russell King - ARM Linux wrote: > On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote: >> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */ >> + >> +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */ >> +#define CTR_CTYPE_SHIFT 24 >> +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT) >> + >> +static inline unsigned int get_ctr(void) >> +{ >> + unsigned int ctr; >> + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); >> + return ctr; >> +} >> + >> +static enum cache_type get_cache_type(int level) >> +{ >> + if (level > MAX_CACHE_LEVEL) >> + return CACHE_TYPE_NOCACHE; >> + return get_ctr() & CTR_CTYPE_MASK ? >> + CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED; > > So, what do we do for CPUs that don't implement the CTR? Just return > random rubbish based on decoding the CPU Identity register as if it > were the cache type register? > I assume you referring to some particular CPUs which don't implement this. I could not find it as optional or IMPLEMENTATION defined in ARM ARM. I might be missing to find it or there may be exceptions. Can you please provide more information on that ? Regards, Sudeep