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Date:   Tue, 21 Jan 2014 14:16:23 -0600
From:   "Steven J. Hill" <Steven.Hill@imgtec.com>
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To:     David Daney <ddaney.cavm@gmail.com>
CC:     LMOL <linux-mips@linux-mips.org>
Subject: Re: [PATCH] MIPS: lib: Optimize partial checksum ops using prefetching.
References: <1390321122-25634-1-git-send-email-Steven.Hill@imgtec.com> <52DEBBA6.9070701@gmail.com>
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On 01/21/2014 12:25 PM, David Daney wrote:
> On 01/21/2014 08:18 AM, Steven J. Hill wrote:
>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>>
>> Use the PREF instruction to optimize partial checksum operations.
>>
>> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
>
> NACK.  The proper latench and cacheline stride vary by CPU, you cannot
> just hard code them for 32-byte cacheline size with some random latency.
>
> This will make some CPUs slower.
>
Note that memcpy.S already uses fixed cache lines (32 bytes) so this is 
merely doing the same thing. I assume you have some empirical evidence 
concerning other CPUs being slower?