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Message-ID: <52DEE0A9.4010007@gmail.com>
Date:   Tue, 21 Jan 2014 13:03:37 -0800
From:   David Daney <ddaney.cavm@gmail.com>
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To:     "Steven J. Hill" <Steven.Hill@imgtec.com>
CC:     Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: lib: Optimize partial checksum ops using prefetching.
References: <1390321122-25634-1-git-send-email-Steven.Hill@imgtec.com> <20140121204938.GW14169@linux-mips.org> <52DEDF84.1000006@imgtec.com>
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On 01/21/2014 12:58 PM, Steven J. Hill wrote:
> On 01/21/2014 02:49 PM, Ralf Baechle wrote:
>> On Tue, Jan 21, 2014 at 10:18:42AM -0600, Steven J. Hill wrote:
>>
>>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>>>
>>> Use the PREF instruction to optimize partial checksum operations.
>>
>> Prefetch operations may cause obscure bus error exceptions on some
>> systems
>> such as Malta, for example, when prefetching beyond the end of memory.
>> It may also mean memory regions that are just undergoing a DMA transfer
>> are being brought back into cache.
>>
>> This pretty much means that pref is only safe to use on cache-coherent
>> systems.
>>
> So, could we have:
>
>     #ifdef CONFIG_DMA_NONCOHERENT
>     #undef CONFIG_CPU_HAS_PREFETCH
>     #endif
>     #define PREFSIZE   (1 << MIPS_L1_CACHE_SHIFT)
>
> and then use the PREFSIZE value instead of the hardcoded value of 32?

See arch/mips/mm/page.c for code that tries to do something sensible 
with streaming prefetches.


>
> Steve
>
>
>
>