From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 21 Jan 2014 14:54:59 -0800 Subject: [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL In-Reply-To: <1389319859-18547-2-git-send-email-Po.Liu@freescale.com> References: <1389065844-5391-1-git-send-email-Po.Liu@freescale.com> <1389319859-18547-1-git-send-email-Po.Liu@freescale.com> <1389319859-18547-2-git-send-email-Po.Liu@freescale.com> Message-ID: <52DEFAC3.5010507@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 01/09/2014 06:10 PM, Po Liu wrote: > Using the TPL/SPL method to booting from 8k page NAND flash. > - Add 256kB size SRAM tlb for second step booting; > - Add spl.c for TPL image boot; > - Add spl_minimal.c for minimal SPL image; > - Add C29XPCIE_NAND configure; > - Modify C29XPCIE.h for nand config and enviroment; > > Signed-off-by: Po Liu > --- > changes for v2: > - seperate the public code and c29xpcie board code; > changes for v3: > - booting log simple to "SPL" "TPL" > - remove the 8k TLB from 0xffffe000 to 0xffffffff > - change the ddr tlb mapping condition > changes for v4: > - None. > changes for v5: > - code style change. > changes for v6: > - none Applied to u-boot-mpc85xx master branch. Awaiting upstream. York