From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Wed, 22 Jan 2014 16:26:19 -0700 Subject: [U-Boot] [PATCH] ARM: tegra: don't exceed AVP limits when configuring PLLP In-Reply-To: <1390422075-32061-1-git-send-email-swarren@wwwdotorg.org> References: <1390422075-32061-1-git-send-email-swarren@wwwdotorg.org> Message-ID: <52E0539B.3090401@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 01/22/2014 01:21 PM, Stephen Warren wrote: > From: Jimmy Zhang > > Based on the Tegra114 TRM, the system clock (which is the AVP clock) can > run up to 275MHz. On power on, the default sytem clock source is set to > PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to > 408MHz which is beyond system clock's upper limit. > > The fix is to set the system clock to CLK_M before initializing PLLP, > and then switch back to PLLP_OUT4, which has an appropriate divider > configured, after PLLP has been configured > > Signed-off-by: Jimmy Zhang > [swarren, significantly refactored the changes, so that AVP only runs on > clk_m for the short duration that PLLP is being reconfigured. Fixed > Tegra30 too] I think I need to revise this one patch; while going through the Tegra124 patches, I found function adjust_pllp_out_freqs(), which really should be used by this patch.