From: "Andreas Färber" <afaerber@suse.de>
To: Peter Maydell <peter.maydell@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Subject: Re: [Qemu-devel] QEMU ARM946 emulation, DIGIC, and MPU fault handling
Date: Fri, 24 Jan 2014 00:36:15 +0100 [thread overview]
Message-ID: <52E1A76F.1080802@suse.de> (raw)
In-Reply-To: <CAFEAcA8UF0m3K8p_cOYQ64gRwcxYY5ZxdOX5pAs9dk8APc+MwA@mail.gmail.com>
Am 23.01.2014 23:25, schrieb Peter Maydell:
> This bug would also affect the ARMv7M CPU (Cortex-M3) we emulate,
> except that as far as I can tell we don't implement its MPU interface at all!
> (it uses memory mapped registers rather than cp15 regs, and they just
> aren't wired up in armv7m_nvic.c...)
That matches my memories of investigating Cortex-R4. There is some MPU
code present somewhere, but it appeared to be for some older CPU,
possibly OMAP2.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2014-01-23 23:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-23 22:25 [Qemu-devel] QEMU ARM946 emulation, DIGIC, and MPU fault handling Peter Maydell
2014-01-23 23:36 ` Andreas Färber [this message]
2014-01-23 23:52 ` Peter Maydell
2014-01-24 8:31 ` Antony Pavlov
2014-01-25 9:13 ` Georg Hofstetter
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