From: "Andreas Färber" <afaerber@suse.de>
To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: Edgar Iglesias <edgar.iglesias@xilinx.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@xilinx.com>
Subject: Re: [Qemu-devel] [PATCH target-arm v5 4/5] arm: Implement reset GPIO.
Date: Tue, 28 Jan 2014 10:28:20 +0100 [thread overview]
Message-ID: <52E77834.8010004@suse.de> (raw)
In-Reply-To: <CAEgOgz6WP7fomCZNOVWE1chhR38Mr_YAbs8vYZt=9b20DQxfRA@mail.gmail.com>
Hi,
Am 28.01.2014 01:48, schrieb Peter Crosthwaite:
> On Tue, Jan 28, 2014 at 3:52 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> Is there anything really ARM-specific in this reset_gpio
>> function, or could it be implemented at a common level for
>> all target architectures?
>>
>
> Not yet, but probably will be ARM specific once I add the cpu reset
> pin state. Unless Andreas is happy for that pin state and all this
> code to go up to the base TYPE_CPU class.
>
> I wonder however, whether different arch will have level/edge/high/low
> variances in reset behavior that must be accommodated.
>
> Andreas, you want this in CPU or should we leave it here in ARM land?
I'm currently swimming in work, so haven't really reviewed this yet...
If you have a good solution that requires additions to common CPU state
then so be it. However, keep in mind that for x86 at least we need to
remain migration-compatible, so state additions would need to go into an
optional VMState subsection for backwards compatibility.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2014-01-28 9:28 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-15 9:12 [Qemu-devel] [PATCH target-arm v5 0/5] Reset and Halting modifications + Zynq SMP Peter Crosthwaite
2014-01-15 9:13 ` [Qemu-devel] [PATCH target-arm v5 1/5] arm: zynq: Macroify OCM Base and Size Peter Crosthwaite
2014-01-27 17:41 ` Peter Maydell
2014-01-15 9:13 ` [Qemu-devel] [PATCH target-arm v5 2/5] arm: zynq: added SMP support Peter Crosthwaite
2014-01-27 17:42 ` Peter Maydell
2014-01-15 9:14 ` [Qemu-devel] [PATCH target-arm v5 3/5] zynq_slcr: Implement CPU reset Peter Crosthwaite
2014-01-27 17:43 ` Peter Maydell
2014-01-15 9:14 ` [Qemu-devel] [PATCH target-arm v5 4/5] arm: Implement reset GPIO Peter Crosthwaite
2014-01-27 17:52 ` Peter Maydell
2014-01-28 0:48 ` Peter Crosthwaite
2014-01-28 9:22 ` Peter Maydell
2014-02-12 5:20 ` Peter Crosthwaite
2014-01-28 9:28 ` Andreas Färber [this message]
2014-01-15 9:15 ` [Qemu-devel] [PATCH target-arm v5 5/5] arm: zynq: Connect CPU resets to SLCR Peter Crosthwaite
2014-01-24 8:51 ` [Qemu-devel] [PATCH target-arm v5 0/5] Reset and Halting modifications + Zynq SMP Peter Crosthwaite
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=52E77834.8010004@suse.de \
--to=afaerber@suse.de \
--cc=alistair.francis@xilinx.com \
--cc=edgar.iglesias@xilinx.com \
--cc=peter.crosthwaite@xilinx.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.