From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3] mx6: Enable L2 cache support
Date: Tue, 28 Jan 2014 15:58:31 +0100 [thread overview]
Message-ID: <52E7C597.80205@denx.de> (raw)
In-Reply-To: <1390920860-12153-1-git-send-email-fabio.estevam@freescale.com>
On 28/01/2014 15:54, Fabio Estevam wrote:
> Add L2 cache support and enable it by default.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - Add L2_PL310_BASE definition in imx_regs.h
> Changes since v1:
> - Fx typo in commit log
>
> arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
> include/configs/mx6_common.h | 5 +++++
> 3 files changed, 26 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 0208cba..b84de87 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -8,6 +8,8 @@
> */
>
> #include <common.h>
> +#include <asm/armv7.h>
> +#include <asm/pl310.h>
> #include <asm/errno.h>
> #include <asm/io.h>
> #include <asm/arch/imx-regs.h>
> @@ -336,3 +338,21 @@ void imx_setup_hdmi(void)
> writel(reg, &mxc_ccm->chsccdr);
> }
> #endif
> +
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +#define L2CACHE 1
> +void v7_outer_cache_enable(void)
> +{
> + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
> +
> + setbits_le32(&pl310->pl310_ctrl, L2CACHE);
> +
> +}
> +
> +void v7_outer_cache_disable(void)
> +{
> + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
> +
> + clrbits_le32(&pl310->pl310_ctrl, L2CACHE);
> +}
> +#endif /* !CONFIG_SYS_L2CACHE_OFF */
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index f2ad6e9..c2d210a 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -53,6 +53,7 @@
> #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
> #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
> #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
> +#define L2_PL310_BASE 0x00A02000
> #define GPV0_BASE_ADDR 0x00B00000
> #define GPV1_BASE_ADDR 0x00C00000
> #define PCIE_ARB_BASE_ADDR 0x01000000
> diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
> index 514d634..63afa46 100644
> --- a/include/configs/mx6_common.h
> +++ b/include/configs/mx6_common.h
> @@ -22,4 +22,9 @@
> #define CONFIG_ARM_ERRATA_751472
> #define CONFIG_BOARD_POSTCLK_INIT
>
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +#define CONFIG_SYS_L2_PL310
> +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
> +#endif
> +
> #endif
>
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
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next prev parent reply other threads:[~2014-01-28 14:58 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-28 14:54 [U-Boot] [PATCH v3] mx6: Enable L2 cache support Fabio Estevam
2014-01-28 14:58 ` Stefano Babic [this message]
2014-01-28 16:53 ` Dirk Behme
2014-01-28 19:12 ` Fabio Estevam
2014-01-29 12:47 ` Stefano Babic
2014-01-29 17:57 ` Fabio Estevam
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